VLSI Design MCQ Quiz – Objective Question with Answer for VLSI Design MCQ

1. VLSI technology uses ________ to form an integrated circuit.

a) transistors
b) switches
c) diodes
d) buffers

Answer: a
Very large scale integration is the process of creating an integrated circuit with thousands of transistors into one single chip.


2. Medium scale integration has ____________

a) ten logic gates
b) fifty logic gates
c) hundred logic gates
d) thousands logic gates

Answer: c
Small scale integration has one or more logic gates. Further improved technology is medium-scale integration which consists of hundred logic gates. Large-scale integration has thousand of logic gates.


3. The difficulty in achieving high doping concentration leads to ____________

a) error in concentration
b) error in variation
c) error in doping
d) distribution error

Answer: b
As photolithography comes closer to the fundamental law of optics, achieving high accuracy in doping concentration becomes difficult, which leads to error due to variation.


4. _________ is used to deal with effect of variation.

a) chip level technique
b) logic level technique
c) switch level technique
d) system-level technique

Answer: d
Designers must simulate multiple fabrication processes or use system level techniques for dealing with the effects of variation.


5. As die size shrinks, the complexity of making the photomasks ____________

a) increases
b) decreases
c) remains the same
d) cannot be determined

Answer: a
As the die size shrinks due to scaling, the number of dies per wafer increases and the complexity of making the photomasks increases rapidly.


6. ______ architecture is used to design VLSI.

a) system on a device
b) single open circuit
c) system on a chip
d) system on a circuit

Answer: c
SoC which is a system on a chip architecture is used to design a very high-level integrated circuit.


7. What is the design flow of VLSI system?

i. architecture design
ii. market requirement
iii. logic design
iv. HDL coding

a) ii-i-iii-iv
b) iv-i-iii-ii
c) iii-ii-i-iv
d) i-ii-iii-iv


Answer: a

The order of the design flow of VLSI circuit is market requirement, architecture design, logic design, HDL coding and then verification.


8. ______ is used in logic design of VLSI.


Answer: b
First in first out (FIFO) technique and finite-state machine technology is used in the logic design of the VLSI circuits.


9. Which provides higher integration density?

a) switch transistor logic
b) transistor buffer logic
c) transistor transistor logic
d) circuit-level logic

Answer: c
Transistor-transistor logic offers higher integration density and it became the first integrated circuit revolution.


10. Physical and electrical specification is given in ____________

a) architectural design
b) logic design
c) system design
d) functional design

Answer: d
Functional design defines the major functional units of the system, interconnections, and physical and electrical specifications.


11. Which is the high-level representation of VLSI design?

a) problem statement
b) logic design
c) HDL program
d) functional design

Answer: a
The problem statement is a high-level representation of the system. Performance, functionality, and physical dimensions are considered here.


12. Gate minimization technique is used to simplify the logic.

a) true
b) false

Answer: a
The Gate minimization technique is used to find the simplest, smallest and most effective implementation of the logic.


13. nMOS fabrication process is carried out in ____________

A. thin wafer of a single crystal
B. thin wafer of multiple crystals
C. thick wafer of a single crystal
D. thick wafer of multiple crystals

Answer: A
the nMOS fabrication process is carried out in a thin wafer of a single crystal with high purity.


14. ______________ impurities are added to the wafer of the crystal.

A. n impurities
B. p impurities
C. siicon
D. crystal

Answer: B
p impurities are introduced as the crystal is grown. This increases the hole concentration in the device.


15. What kind of substrate is provided above the barrier to dopants?

A. insulating
B. conducting
C. silicon
D. semiconducting

Answer: A
Above a layer of silicon dioxide which acts as a barrier, an insulating layer is provided upon which other layers may be deposited and patterned.


16. The photoresist layer is exposed to ____________

A. Visible light
B. Ultraviolet light
C. Infra red light

Answer: B
The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion is to take place.


17. In nMOS device, gate material could be ____________

A. silicon
B. polysilicon
C. boron
D. phosphorus

Answer: B
In nMOS device, the gate material could be metal or polysilicon. This polysilicon layer has heavily doped polysilicon deposited by CVD.


18. Which is the commonly used bulk substrate in nMOS fabrication?

A. silicon crystal
B. silicon-on-sapphire
C. phosphorus
D. silicon-di-oxide

Answer: C
In nMOS fabrication, the bulk substrate used can be either bulk silicon or silicon-on-sapphire.


19. In nMOS fabrication, etching is done using ____________

A. plasma
B. hydrochloric acid
C. sulphuric acid
D. sodium chloride

Answer: A
In nMOS fabrication, etching is done using hydrofluoric acid or plasma. Etching is a process used to remove layers from the surface.


20. Heavily doped polysilicon is deposited using ____________

A. chemical vapour decomposition
B. chemical vapour deposition
C. chemical deposition
D. dry deposition

Answer: B
The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapour deposition.


21. In diffusion process ______ impurity is desired.

A. n-type
B. p-type
C. np type
D. none of the mentioned

Answer: A
Diffusion is carried out by heating the wafer to a high temperature and passing a gas containing the desired n-type impurity.


22. Contact cuts are made in ____________

A. source
B. drain
C. metal layer
D. diffusion layer

Answer: A
Contact cuts are made in the desired polysilicon area, source and gate. COntact cuts are those places where a connection has to be made.


23. Interconnection pattern is made on ____________

A. polysilicon layer
B. silicon-di-oxide layer
C. metal layer
D. diffusion layer

Answer: C
The metal layer is masked and etched to form an interconnection pattern. The metal layer was formed using aluminium deposited over the formed surface.


24. SIlicon-di-oxide is a good insulator.
A. true
B. false

Answer: A
SIlicon-di-oxide is a very good insulator so a very thin layer is required in the fabrication of a MOS transistor.


25. _______ is used to suppress unwanted conduction.

A. phosphorus
B. boron
C. silicon
D. oxygen

Answer: B
Boron is used to suppress the unwanted conduction between transistor sites. It is implanted in the exposed regions.


26. Which is used for the interconnection?

A. boron
B. oxygen
C. aluminium
D. silicon

Answer: C
Aluminium is the suitable material used for the circuit interconnection or connecting two layers.

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