A. logic circuit design
B. topology of the communication
C. color codes of the layers
D. functions of layers
Answer: B
Design is largely a matter of topology of communication rather than the detailed logic circuit design.
2. To minimize the design effort, regularity should be
A. low
B. high
C. very low
D. very high
Answer: B
Regularity is a qualitative parameter and it should be high as possible to minimize the design effort required for any system.
3. Regularity is the ratio of
A. total transistors in the chip to total transistors that must be designed in detail
B. total transistors that must be designed in detail to total transistors in a chip
C. total transistors to total components
D. total charge storage components to charge dissipating components
Answer: A
Regularity is the ratio of total transistors in the chip to total transistors that must be designed in detail.
4. Good design system has regularity in the range of
A. 25-50
B. 50-75
C. 50-100
D. 25-50
Answer: C
A good design system must have regularity in the range of 50 to 100 or more and regular structures such as memories achieve very high figures.
5. In the adder, the sum is stored in
A. series
B. cascade
C. parallel
D. registers
Answer: C
The sum is stored in parallel at the output of the adder from where it may be fed through the shifter and back to the register array.
6. The shifter must be connected to
A. 2-shift data line
B. 2-shift control line
C. 4-shift data line
D. 4-shift control line
Answer: D
The shifter is unclocked but must be connected to 4 shift control lines. Carry out and Carry in signal must also be connected.
7. What is the sum and carry if the two-bit number is 1 1 and the previous carry is 0?
A. 0, 0
B. 0, 1
C. 1, 0
D. 1, 1
Answer: B
If the two-bit number is 1 1 and the previous carry is 0 the sum is 0 and the carry is 1. This can be obtained by first adding the two numbers 1 and 1. The sum will be 0 and the carry is 1. Later add the previous carry 0 to it. Now the sum is finally 0 and the final carry will be 1.
8. Which design is preferred in the n-bit adder?
A. many pass transistors in series
B. many pass transistors with a suitable buffer
C. many pass transistors without suitable buffer
D. many pass transistors in parallel
Answer: B
In n-bit adder, n adder elements must be cascaded with carrying out connecting to carry in. This carry chain will have more pass transistors connected in series which will give a slow response. Thus suitable buffer can be used in between.
9. In adders, the previous carry can also be given by
A. propagate signal pk
B. generate signal gk
C. pk and gk
D. sk
Answer: C
In adders, the previous carry signal can also be given using propagate signal pk which is ex-or of two bits ak and bk and also using generate signal gk which is ‘and’ of ak and bk.
10. Adder using _______ technology can be used for speed improvement.
A. CMOS
B. BiCMOS
C. nMOS
D. pMOS
Answer: B
Using BiCMOS technology, speed improvement can be obtained by a factor of two over CMOS technology. This arrangement works will lower input voltage swings to achieve higher speed.
