VLSI Design of ALU Subsystem MCQ Quiz – Objective Question with Answer for VLSI Design of ALU Subsystem

11. For carrying skip adder, the minimum total propagation delay can be obtained when m is

A. sqrt(nk1/k2)
B. sqrt(2nk1/k2)
C. sqrt(2k1/nk2)
D. sqrt(nk1k2/2)

Answer: B

For carry skip adder the total propagation delay T is given by 2((n/M)-1)k1 + (M-2)k2. The minimum value of T can be obtained when m is sqrt(2nk1/k2).

 

12. Multiple output domino logic has

A. two cell manchester carry chain
B. three cell manchester carry chain
C. four-cell manchester carry chain
D. four-cell manchester carry look ahead

Answer: C

To reduce the complexity of the carry look-ahead adder, a dynamic logic technique called multiple output domino logic is used. This approach consists of four cell manchester carry chains.

 

13. Multipliers are built using

A. binary adders
B. binary subtractors
C. dividers
D. multiplexers

Answer: A

A multiplier is an electronic circuit used to multiply two binary numbers. It is built using binary adders that are full adders.

 

14. Which method uses a reduced number of partial products?

A. Baugh-Wooley algorithm
B. Wallace trees
C. Dadda multipliers
D. Modified booth encoding

Answer: D

Multiplication in multipliers is done by obtaining partial products and then summing it up. Modified booth encoding reduces the number of partial products that must be summed.

 

15. Which method is easier to manipulate accumulator content?

A. left shifting
B. right shifting
C. serial shifting
D. parallel shifting

Answer: B

It is easier to right shift the contents of the accumulator than to left shift. This can be used to eliminate the least significant bits of the product.

 

16. Which multiplier is very well suited for twos-complement numbers?

A. Baugh-Wooley algorithm
B. Wallace trees
C. Dadda multipliers
D. Modified booth encoding

Answer: A

The Baugh-Wooley method is used to design multipliers that are regular in structure and is very well suited for twos-complement numbers.

 

17. What is the delay required to perform a single operation in a pipelined structure?

A. 2n
B. 3n
C. 4n
D. n

Answer: B

The delay of one operation through the pipeline is 3n that is it takes 3n clock cycles to obtain a product after X and Y are input.

 

18. Latches chosen are

A. static shift registers
B. any flipflop
C. dynamic shift register
D. multiplexers

Answer: C

The latches chosen are dynamic shift registers as the structure will be continuously clocked.

 

19. Which method reduces the number of cycles of operation?

A. Baugh-Wooley algorithm
B. Wallace trees
C. Dadda multipliers
D. Modified booth encoding

Answer: D

The modified booth encoding algorithm avoids many idle cells in a cellular multiplier as well as reduces the number of cycles compared with the serial-parallel multiplier.

 

20. The completion time for multiplication time in the Baugh-Wooley method is

A. n
B. 2n
C. 3n
D. 4n

Answer: B

The completion time for multiplication in Braun or Baugh-Wooley is proportional to 2n whereas completion time in the Wallace tree method is proportional to log(base 2)(n).

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