VLSI Design Testability MCQ Quiz – Objective Question with Answer for VLSI Design Testability

21. Single stuck-at fault is technology independent.

A. true
B. false

Answer: A

The single stuck-at fault is technology independent. It can be applied to TTL, CMOS, etc. It is also design style independent.

 

22. For a n signal lines circuit _____________ bridging faults are possible.

A. n
B. 2n
C. n2
D. n/2

Answer: C

For circuits with n lines, n2 bridging faults are possible. The bridging fault occurs when two lines are connected when they should not be connected. It leads to wired AND or wired OR.

 

23. IDDQ fault occurs when there is

A. increased voltage
B. increased quiescent current
C. increased power supply
D. increased discharge

Answer: B

When the input is low, both P and N transistors are conducting causing an increase in quiescent current which leads to IDDQ fault.

 

24. Which fault causes output floating?

A. stuck-open
B. stuck-at
C. stuck-on
D. IDDQ

Answer: A

Transistor with stuck-open fault causes output floating. Stuck-open faults require two vector tests.

 

25. Data retention time comes under __________ fault.

A. functional fault
B. memory fault
C. parametric fault
D. structural fault

Answer: C

One of the memory faults is a parametric fault. Some of the parametric faults are noise margin, data retention time, power consumption, output levels, etc.

 

26. In PLA, missing the cross point in OR-array leads to

A. OR fault
B. growth fault
C. missing fault
D. disappearance fault

Answer: D

In PLA, missing the cross point in AND array leads to growth fault and missing cross point in OR-array leads to disappearance fault.

 

27. In PLA, extra crosspoint in AND-array leads to

A. OR fault
B. growth fault
C. missing fault
D. disappearance fault

Answer: D

In PLA, extra crosspoint in AND-array leads to shrinkage or disappearance fault whereas extra crosspoint in OR-array leads to appearance fault.

 

28. The number of paths ___________ with number of gates.

A. increases exponentially
B. decreases exponentially
C. remains the same
D. increases rapidly

Answer: A

The number of paths increases exponentially with the number of gates. The propagation delay of the path exceeds the clock interval.

 

29. The quality of the test set is measured by

A. fault margin
B. fault detection
C. fault correction
D. fault coverage

Answer: D

The quality of a test set is measured by its fault coverage. It gives the fraction of faults that is detected by the test set.

Scroll to Top