1. For shorter delays ______ resistance should be used.

A. smaller
B. larger
C. does not depend on the resistance
D. very large

Answer: A

For shorter delays, low resistance should be used as delay is directly proportional or related to resistance.

2. To reduce the resistance value of inverters, channels must be made __________

A. wider
B. narrower
C. lengthier
D. shorter

Answer: A

Channels must be made wider to reduce the resistance value that is low resistance values for Zp.u. ad Zp.d. implies low L: W ratios and thus consequently an inverter to meet this need occupies a larger area.

3. As width increases, capacitive load __________

A. increases
B. decreases
C. does not change
D. exponentially increases

Answer: A

As the width of the channel increases, capacitive load also increases and with this, the area occupied also increases. The rate at which the width increases affects the stages N and load capacitance.

4. Delay per stage for logic 0 to 1 transition can be given as __________

A. fƮ
B. 2fƮ
C. 3fƮ
D. 4fƮ

Answer: A

Delay per stage for logic 0 to 1 transition can be given as fƮ. With large f, N decreases but delay per stage increases.

5. Delay per stage for logic 1 to 0 transition can be given as __________

A. fƮ
B. 2fƮ
C. 3fƮ
D. 4fƮ

Answer: D

Delay per stage for logic 1 to 0 transition can be given as 4fƮ. Using the delay for the transition from 1 to 0 and 0 to 1 total nMOS delay can be obtained.

6. What is the total delay of an nMOS pair?

A. fƮ
B. 2fƮ
C. 5fƮ
D. 4fƮ

Answer: C

The total delay of an nMOS pair is equal to 5fƮ. This can be calculated by knowing the delay per stage, that is for two different transitions from 0 to 1 and vice versa.

7. What is the total delay of a CMOS pair?

A. 5fƮ
B. 7fƮ
C. 8fƮ
D. 4fƮ

Answer: B

The total delay of a CMOS pair is equal to 7fƮ. This can be calculated by knowing the delay per stage of CMOS.

8. The number of stages N can be given as ______

A. ln(y)*ln(f)
B. ln(y)/ln(f)
C. ln(f)/ln(y)
D. ln(f)/ln(2y)

Answer: B

The number of stages N can be given as ln(y)/ln(f). By knowing whether the number of stages N is even or odd we can calculate the total delay for nMOS, CMOS, etc.

9. When the number of stages N is even, the total delay for nMOS can be?

A. 1.5NfƮ
B. 2.5NfƮ
C. 3.5NfƮ
D. 4.5NfƮ

Answer: B

When the number of stages N is even, the total delay for nMOS can be given as 2.5NfƮ. This is calculated by using the formula (N/2)*5fƮ.

10. When the number of stages N is even, the total delay for CMOS can be?
A. 1.5NfƮ
B. 2.5NfƮ
C. 3.5NfƮ
D. 4.5NfƮ

Answer: C

When the number of stages N is even, the total delay for CMOS can be given as 3.5NfƮ. This is calculated by using the formula (N/2)*7fƮ.