A. depletion mode MESFET
B. enhancement mode MESFET
C. depletion-mode FET
D. enhancement mode FET
Answer: B
Normally-on logic uses depletion-mode MESFETs which are ON devices and when used as switching elements are required to be turned OFF.
2. Which is the approach used for normally-off logic?
A. capacitor diode FET logic
B. buffered FET logic
C. direct-coupled FET logic
D. capacitor coupled FET logic
Answer: C
The approaches used for normally-off logic are direct-coupled FET logic, buffered DCFL, and source-follower DCFL.
3. __________ is needed to facilitate turn-off.
A. positive voltage
B. power supply rail
C. ground connection
D. negative voltage
Answer: D
Since D-MESFETs are ON devices, a negative voltage is needed at the gate to facilitate turn-off.
4. __________ supply rails are required for proper operation of normally-on logic devices.
A. one
B. two
C. three
D. four
Answer: B
Two supply rails together with level shifting networks are necessary for proper circuit operation of normally-on logic gates.
5. In direct coupled FET logic, both depletion and enhancement mode devices are used.
A. true
B. false
Answer: A
In direct-coupled FET logic, both the depletion mode and enhancement mode transistors are used. Enhancement mode FET is used as the switching element and depletion mode FET is used as load.
6. DCFL circuits have
A. large voltage swing
B. small voltage swing
C. large noise margins
D. more complexity
Answer: B
In direct-coupled FET logic, only small voltage swings are possible and also relatively small noise margins.
7. Which circuits have weak load drive capability?
A. DCFL
B. DCFL with super buffers
C. FET logic
D. SDCFL
Answer: A
DCFL circuits have weak load drive capability. This can be improved by the introduction of super buffers with the expense of extra area.
8. Which logic is suitable for large loads?
A. DCFL
B. DCFL with super buffers
C. FET logic
D. SDCFL
Answer: B
DCFL with super buffers is used for larger loads to be driven whereas DCFL circuits are used for light load conditions.
9. Which circuit has a large noise margin?
A. DCFL
B. DCFL with super buffers
C. FET logic
D. SDCFL
Answer: D
Source follower DCFL FET logic has power dissipation and also switching delay. This has a larger noise margin which is due to the pull-up transistor being able to be turned off.
10. Which logic is suitable for the And-OR-Invert function?
A. DCFL
B. DCFL with super buffers
C. FET logic
D. SDCFL
Answer: D
The source-follower DCFL FET logic is most suitable for the realization of the And-OR-Invert function which usually assists in the optimization of logical functions.
