21. In CMOS domino logic _______ is possible.
A. inverting structure
B. non-inverting structure
C. inverting and non-inverting structure
D. very complex design
21. Clocked sequential circuits are
A. two-phase overlapping clock
B. two-phase non-overlapping clock
C. four-phase overlapping clock
D. four-phase non-overlapping clock
22. Which are easier to design?
A. clocked circuits
B. asynchronous sequential circuits
C. clocked circuits with buffer
D. asynchronous sequential circuits with buffers
23. ___________ is used to drive high capacitance load.
A. single polar capability
B. bipolar capability
C. tripolar capability
D. bi and tripolar capability
24. As the temperature is increased, storage time ________
A. halved
B. doubled
C. does not change
D. tripled
25. Inverting dynamic register element consists of __________ transistors for nMOS and _________ for CMOS.
A. two, three
B. three, two
C. three, four
D. four, three
26. Non inverting dynamic register storage cell consists of _________ transistors for nMOS and _________ for CMOS.
A. six, eight
B. eight, six
C. five, six
D. six, five
27. Register cell consists of
A. inverter
B. pass transistor
C. inverter & pass transistor
D. none of the mentioned
28. In a four-bit dynamic shift register basic nMOS transistors or inverters are connected in
A. series
B. cascade
C. parallel
D. series and parallel
29. In four-bit dynamic shift register output is obtained
A. parallel output at inverters 1, 3, 5, 7
B. parallel output at inverters 1, 5, 8
C. parallel output at all inverters
D. parallel output at inverters 2, 4, 6, 8
30. For signals which are updated frequently _____ is used.
A. static storage
B. dynamic storage
C. static and dynamic storage
D. buffer