VLSI layout floor plan MCQ Quiz – Objective Question with Answer for VLSI layout floor plan

11. Buffers are needed to drive

A. small capacitance
B. large capacitance
C. small resistance
D. large resistance

Answer: B

Buffers are necessary for environments on and off-chip. It is used to drive relatively large capacitances associated with circuits of the chip.


12. Pads must be placed generally in the periphery of the chip area.

A. true
B. false

Answer: A

Usually, pads must be placed in the periphery of the chip area otherwise bonding difficulties may be encountered.


13. How much area should be allocated for pads?

A. one third
B. two-third
C. half
D. three fourth

Answer: A

According to a thumb rule, the small system designer should allow one-third of the chip area for pads.


14. Which provides large capacitance?

A. load capacitance
B. bus wiring capacitance
C. sheet capacitance
D. area capacitance

Answer: B

Bus wiring capacitance Cbus provides the largest capacitance for a typical bus system for example for small chips this can be as high as 0.8pF.


15. Bus wiring capacitance is driven through

A. one transistor
B. two transistors
C. three transistors
D. no transistors

Answer: A

Bus wiring capacitance is driven through pull-up and pull-down transistors and through at least one pass transistor or transmission gate in the series.


16. What is the delay of input pads?

A. 5Ʈ
B. 10Ʈ
C. 40Ʈ
D. 30Ʈ

Answer: D

The input pad always contains overvoltage protection circuitry and Schmitt trigger circuitry. Its total delay is 30Ʈ.


17. The total delay for the select register circuit is

A. 33Ʈ
B. 60Ʈ
C. 55Ʈ
D. 73Ʈ

Answer: D

The total delay for the select register is 73Ʈ. It is the sum of delays of the input pad, three pass transistors, and driver inverter pair.


18. Delay for data propagation is

A. 10 nsec
B. 50 nsec
C. 100 nsec
D. 150 nsec

Answer: C

Data is propagated through the bus. The bus can be bidirectional but data can be propagated through the bus only in one direction at a time. The delay for this data propagation is 100 nsec.


19. Which is the longest delay in the adder process?

A. sum delay
B. carry delay
C. propagation delay
D. inverter delay

Answer: B

The longest delay in the adder process is the carry chain delay. This is the process of forming carry out which propagates through all bits of the adder.


20. The total delay for the adder process is

A. 100 nsec
B. 200 nsec
C. 220 nsec
D. 250 nsec

Answer: C

The total delay for the adder process is 220 nsec. The total delay is the sum of select register delays, bus delays, and carries chain delays.

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