A. deterministic test patterns
B. algorithmic test patterns
C. random test patterns
D. pseudo-random test patterns
Answer: B
Finite state machines are used for algorithmic test pattern generation testing for the circuit under test.
282. Address ordering minimizes the logic of finite state machines.
A. true
B. false
Answer: A
Address ordering in either ascending or descending order in the first and last loop minimizes the logic of finite state machines.
283. In finite state machine the data in and data out are
A. in the same ports
B. different ports
C. same register
D. different register
Answer: B
In finite state machines, there are separate ports for DATA IN and DATA OUT and this is a typical RAM structure.
284. _______ is used to control the read and write operations.
A. active low synchronous reset
B. active high synchronous reset
C. active low synchronous preset
D. active high synchronous preset
Answer: B
With the use of active high synchronous reset (clear) read and write operations in a finite state machine can be done.
285. Finite state machine will initially set to all zeroes.
A. true
B. false
Answer: A
The finite state machine has an initial state initialized with all 0’s whereas LFSR and CA have an initial state with any state other than all 0’s.
286. Fault coverage is ______ in finite state machines.
A. less
B. more
C. equal
D. none of the mentioned
Answer: B
The fault coverage and area overhead are better when the initial state is initialized to all 0’s in finite state machine.
287. Which exhibits low fault coverage?
A. random test pattern
B. pseudo-random test pattern
C. deterministic test pattern
D. algorithmic test pattern
Answer: B
The circuit under test exhibits low fault coverage when tested with the pseudo-random test generation method.
288. Large AND function will produce _______ infrequently.
A. logic 0
B. logic 0 and logic 1
C. logic 1
D. neither logic 0 or 1
Answer: C
The large AND function produces logic 1 infrequently due to its equally likelihood of more 0’s whereas the large OR function produces logic 0 infrequently.
289. The circuit which incorporates _______ can be tested with a weighted pseudo-random test pattern.
A. preset
B. reset
C. clear
D. break
Answer: A
The circuit under test which incorporates global reset or preset can be tested with a pseudo-random test pattern method.
290. Circuits with global reset have fault coverage in the range of
A. 5% to 10%
B. 11% to 15%
C. 15% to 20%
D. 6% to 8%
Answer: B
The circuit under test with global reset has fault coverage as low as 11% to 15% due to its fault detection blocking effect.
291. The probability of a given bit in LFSR being logic 0 is
A. 0
B. 1
C. 0.25
D. 0.5
Answer: D
The probability of a given bit in LFSR being logic 0 is approximately 0.5 and NANDing two bits of LFSR gives the probability as 0.25.
292. Initialization of the test pattern generator to all 1’s generate
A. global reset
B. clear
C. toggle
D. buffer
Answer: A
The initialization of the test pattern generator to all 1’s generates a global reset or preset during the first test vector for the initialization of the circuit under test.
293. Reset signal weight is given as
A. 2m
B. 2(-m)
C. 2m
D. 2(-m)
Answer: B
The rule of thumb is to make the reset signal weight as 2(-m) where m is chosen to be greater than the sequential depth of the circuit under test.
294. The sequential depth is the number of
A. OR gates
B. AND gates
C. flip flops
D. EX-OR gates
Answer: C
The sequential depth of the circuit under test is the number of flip flops in the longest path between primary input and output.
295. AND gate is used to ensure whether the test patterns have sufficient clock cycles.
A. true
B. false
Answer: B
NAND gate or NOR gate helps to ensure whether the test patterns have sufficient clock cycles to propagate through the circuit under test before the reset occurs.
296. Which method has more area overhead?
A. random test pattern
B. pseudo-random test pattern
C. algorithmic test pattern
D. deterministic test pattern
Answer: B
The pseudo-random test pattern method has more area overhead along with increased design time. These are the limitations of this method.
297. Pseudorandom testing can determine the test length.
A. true
B. false
Answer: A
Pseudo-random testing can also determine the relationship between test confidence, fault coverage, fault detectability, and test length can also be determined.
298. The pseudo-random testing has
A. high cost
B. less development time
C. low cost but more testing time
D. low cost and less testing time
Answer: B
The pseudo-random testing method has less development time and low development cost. This can be balanced with increased test length.
299. In pseudo-random testing, the test length should be ________ the exhaustive test.
A. lesser than
B. greater than
C. more than
D. none of the mentioned
Answer: A
In pseudo-random testing, the test length should be less than that of the exhaustive test (its upper bound. or the test length will be prohibited for most circuits. This makes pseudo-random testing practical.
300. Pseudo-random testing method involves
A. homogeneous Bernoulli process
B. non-homogeneous Bernoulli process
C. repeatable Bernoulli process
D. non-repeatable Bernoulli process
Answer: B
The most accurate method involved in test pattern generation is the non-homogeneous Bernoulli process. This is called as a pseudo-random testing method.
