A. pseudo-random testing
B. random testing
C. LFSR
D. cellular automata
Answer: A
The pseudo-random testing method gives more accurate results than the random testing method. Its test length estimation is smaller and test quality is better.
302. The fault coverage in a pseudo-random test is determined using
A. fault detection
B. fault removal
C. fault simulation
D. fault distribution
Answer: C
The fault coverage in a pseudo-random test can be determined by using fault simulation. The fault coverage is the measure used to rate the algorithmically generated test set.
303. Faults causing the largest loss of coverage are those with
A. smallest detectability
B. largest detectability
C. all of the mentioned
D. none of the mentioned
Answer: A
Faults causing the largest loss of coverage are those with the smallest detectability. These faults are counted in the initial nonzero elements of the detectability profile.
304. With a test sequence of length zero, fault coverage is
A. maximum
B. 1
C. 0
D. cannot be determined
Answer: C
With a test sequence of length zero, the fault coverage is 0 and each fault is responsible for fault coverage loss regardless of its detectability.
305. Upper bound fault is the fault with detectability
A. 0
B. 1
C. maximum
D. minimum
Answer: B
Upper bound fault is the fault with detectability k=1 and it is used where the detectability profile of the circuit under test is unknown.
306. To reduce the size mismatch, test length is minimized.
A. true
B. false
Answer: A
If the size of the pseudo-random test generator does not match the size of the circuit under test, a size mismatch occurs. This can be compromised by reducing the test length.
307. The test pattern generator which uses a shift register along with LFSR is of __________ bits.
A. N
B. M
C. N+M
D. N*M
Answer: C
The test pattern generator uses an M-bit shift register with N-bit LFSR, the test pattern generator is of N+M bits.
308. The N+M bit test pattern generator has __________ different patterns produced.
A. 2(N+M)
B. 2N+M
C. 2NM
D. 2M+N
Answer: B
The N+M bit test pattern generator can produce a maximum of 2N+M possible different patterns during its first cycle.
309. Which property can prevent high fault coverage?
A. fault limit
B. clock fault
C. linear interleading
D. linear dependencies
Answer: D
The test pattern generated in this method will contain an additional property called linear dependencies that can prevent high fault coverage in some circuits.
310. __________ are used along with flip-flops to build accumulators.
A. adders
B. multipliers
C. buffers
D. AND gates
Answer: A
Adders can be used in conjunction with the flip-flops to construct an accumulator that functions in test pattern generators.
311. What is the desired constant value to be used with the initial values?
A. 0
B. 1
C. N
D. M
Answer: B
The constant value 1 can always be used with any initial value for a register to ensure that the accumulator increments through all combinations of test patterns.
312. Which can be used to check the working of the accumulator?
A. adder
B. shifter
C. multiplier
D. counter
Answer: D
The counter would be more area-efficient in testing whether accumulator increments through all combinations.
313. Test patterns produced by ________ have both high and least toggle rates.
A. random pattern generator
B. counters
C. LFSR
D. CA
Answer: B
Test patterns generated by counters have least and high toogle rates of the least and most significant bits respectively.
314. Which method does not have to carry out?
A. LFSR
B. CA
C. Counters
D. Random sequence generator
Answer: C
The counter is an 8-bit binary up counter with active high count enabled but with no carry-out.
315. Which method is easiest to test?
A. LFSR
B. Counter
C. CA
D. Weighted LFSR
Answer: A
LFSR method is the most area-efficient method and is also the easiest method to test. This is its most important advantage.
316. Which requires more number of cycles for 100% fault coverage?
A. internal feedback LFSR
B. external feedback LFSR
C. weighted LFSR
D. ca
Answer: B
External feedback LFSR takes more number of cycles for 100% fault coverage than internal feedback LFSR and CA methods.
317. The detectability profile can be determined using
A. D algorithm
B. Cellular automata
C. LFSR
D. Random testing
Answer: A
The detectability of every fault in the circuit fault is needed for better testing. To determine this detectability profile, the D algorithm is used which gives accurate results.
318. Automatic test pattern generator detects only the fault and not its cause.
A. true
B. false
Answer: B
The test patterns generated using an automatic test pattern generator are used to detect the faults and in some cases, it assists in finding the cause of the failure too.
319. The automatic test pattern generator method has ________ phases.
A. two
B. three
C. four
D. five
Answer: A
The automatic test pattern generator method has two phases – fault activation and fault propagation phase.
320. Faults that produce the same faulty behavior are known as
A. similar faults
B. equivalent faults
C. correlative faults
D. ambiguous faults
Answer: B
Two or more faults may produce the same faulty behavior for all input patterns and these faults are known as equivalent faults.
321. The process of removing equivalent faults is called as
A. equivalent removing
B. bulk damaging
C. fault collapsing
D. fault reduction
Answer: C
The process of removing equivalent faults from the entire set of faults is called as fault collapsing. Any single fault from the whole set of equivalent faults can represent it.
322. ‘n’ signal lines can potentially have _____ stuck-at faults.
A. n2
B. 2n
C. n
D. n/2
Answer: B
If a circuit has n signal lines, then potentially it can have 2n stuck-at faults defined on the circuit.
323. The stuck-at model is a _____ fault model.
A. recurring
B. equivalent
C. simple
D. logical
Answer: D
The stuck-at model is a logical fault model because no delay information is associated with the fault definition.
324. The stuck-at fault is an example of the ______ fault model.
A. transient
B. permanent
C. intermittent
D. simple
Answer: B
Stuck-at fault model is also called a permanent fault model because the faulty effect is assumed to be permanent.
325. Transient faults does not depend on operating condition.
A. true
B. false
Answer: B
Transient faults occur sporadically depending on operating conditions and on the data values on surrounding signal lines.
326. The _________ between two signals is called a bridging fault.
A. open circuit
B. break
C. connection
D. short circuit
Answer: D
A short circuit between two signal lines is called a bridging fault and it is similar to the stuck-at fault model.
327. The sum of all propagation delays along a single path is given as
A. gate delay fault
B. transition fault
C. path delay fault
D. propagation fault
Answer: C
Path delay fault is given as the sum of all propagation faults along a single path. This fault shows that delay of one or more paths exceeds the clock period.
328. Which method is more complex?
A. stuck at fault
B. CA
C. combinational ATPG
D. sequential ATPG
Answer: D
The sequential automatic test pattern generation method is more complex and remains a complex task for large highly sequential circuits.
329. Which are processing faults?
A. missing contact window
B. parasitic transistor
C. oxide breakdown
D. all of the mentioned
Answer: D
Some of the real defects in chips such as processing faults are missing contact windows, parasitic transistors and oxide breakdown.
330. Surface impurities occur due to ion migration.
A. true
B. false
Answer: A
Some of the material defects are bulk defects and surface impurities. Bulk defects are cracks and crystal imperfection and surface impurities occur due to ion migration.
331. Electromigration is a
A. processing fault
B. material defects
C. time-dependent failure
D. packaging fault
Answer: C
Different types of real defects in chips are processing faults, material defects, time-dependent failures, and packaging faults. Time-dependent failures are dielectric breakdown and electromigration.
332. Which relation is correct?
A. failure – error – fault
B. fault – error – failure
C. error – fault – failure
D. error – failure – fault
Answer: B
The relation fault – error – failure is correct. Error is caused by faults and failure which is a deviation of the circuit caused by error.
333. For a circuit with k lines __________ single stuck-at fault is possible.
A. k
B. 2k
C. k/2
D. k2
Answer: B
For a circuit with k lines, 2k single stuck-at faults are possible and 3k – 1 multiple stuck-at faults are possible.
334. Single stuck-at fault is technology independent.
A. true
B. false
Answer: A
The single stuck-at fault is technology independent. It can be applied to TTL, CMOS, etc. It is also design style independent.
335. For a n signal lines circuit _____________ bridging faults are possible.
A. n
B. 2n
C. n2
D. n/2
Answer: C
For circuits with n lines, n2 bridging faults are possible. The bridging fault occurs when two lines are connected when they should not be connected. It leads to wired AND or wired OR.
336. IDDQ fault occurs when there is
A. increased voltage
B. increased quiescent current
C. increased power supply
D. increased discharge
Answer: B
When the input is low, both P and N transistors are conducting causing an increase in quiescent current which leads to IDDQ fault.
337. Which fault causes output floating?
A. stuck-open
B. stuck-at
C. stuck-on
D. IDDQ
Answer: A
Transistor with stuck-open fault causes output floating. Stuck-open faults require two vector tests.
338. Data retention time comes under __________ fault.
A. functional fault
B. memory fault
C. parametric fault
D. structural fault
Answer: C
One of the memory faults is a parametric fault. Some of the parametric faults are noise margin, data retention time, power consumption, output levels, etc.
340. In PLA, missing the cross point in OR-array leads to
A. OR fault
B. growth fault
C. missing fault
D. disappearance fault
Answer: D
In PLA, missing the cross point in AND array leads to growth fault and missing the cross point in OR-array leads to disappearance fault.
341. In PLA, extra crosspoint in AND-array leads to
A. OR fault
B. growth fault
C. missing fault
D. disappearance fault
Answer: D
In PLA, extra crosspoint in AND-array leads to shrinkage or disappearance fault whereas extra crosspoint in OR-array leads to appearance fault.
342. The number of paths ___________ with number of gates.
A. increases exponentially
B. decreases exponentially
C. remains the same
D. increases rapidly
Answer: A
The number of paths increases exponentially with a number of gates. The propagation delay of the path exceeds the clock interval.
343. The quality of the test set is measured by
A. fault margin
B. fault detection
C. fault correction
D. fault coverage
Answer: D
The quality of a test set is measured by its fault coverage. It gives the fraction of faults that is detected by the test set.
344. Design for testability is considered in the production of chips because:
A. Manufactured chips are faulty and are required to be tested
B. The design of chips is required to be tested
C. Many chips are required to be tested within a short interval of time which yields timely delivery for the customers
D. All of the mentioned
Answer: C
Design for testability is considered in production for chips because many chips are required to be tested within a short interval of time which yields timely delivery for the customers.
345. The functions performed during chip testing are:
A. Detect faults in fabrication
B. Detect faults in design
C. Failures in functionality
D. All of the mentioned
Answer: D
The functions performed during chip testing are detecting faults in fabrication and design failures in functionality.
346. ATPG stands for:
A. Attenuated Transverse wave Pattern Generation
B. Automatic Test Pattern Generator
C. Aligned Test Parity Generator
D. None of the mentioned
Answer: B
ATPG is an Automatic Test Pattern Generator.
347. Delay fault is considered as:
A. Electrical fault
B. Logical fault
C. Physical defect
D. None of the Mentioned
Answer: B
Delay fault is considered a logical fault.
348. A metallic blob present between the drain and the ground of the n-MOSFET inverter acts as:
A. Physical defect
B. Logical fault as output is stuck on 0
C. Electrical fault as resistor short
D. All of the mentioned
Answer: D
A metallic blob present between the drain and the ground of the n-MOSFET inverter acts as a Physical defect, a Logical fault as output is stuck on 0, Electrical fault as resistor short.
349. High resistance short present between drain and ground of n-MOSFET inverter acts as:
A. Pull up delay error
B. Logical fault as output is stuck at 1
C. Electrical fault as transistor stuck on
D. All of the mentioned
Answer: A
High resistance short present between drain and ground of n-MOSFET inverter acts as Pull up delay error.
350. The defect present in the following MOSFET is:
A. Logical stuck at 1
B. Logical stuck at 0
C. Physical defect
D. Electrical Transistor stuck open
Answer: D
The dimensions of the gate are less than the distance between source and drain.
351. The fault simulation detects faults by:
A. Test generation
B. Construction of fault Dictionaries
C. Design analysis under faults
D. All of the mentioned
Answer: D
The fault simulation detects faults by
Test generation
Construction of fault Dictionaries
Design analysis under faults
352. The ease with which the controller establishes specific signal values at each node by setting input values is known as:
A. Testability
B. Observability
C. Controllability
D. Manufacturability
Answer: C
Controllability is defined as the ease with which the controller establishes a specific signal value at each node by setting input values.
353. The ease with which the controller determines signal value at any node by setting input values is known as:
A. Testability
B. Observability
C. Controllability
D. Manufacturability
Answer: B
Observability is defined as the ease with which the controller determines signal value at any node by setting input values.
354. The poor controllability circuits are:
A. Decoders
B. Clock generators
C. Circuits with feedback
D. All of the mentioned
Answer: D
The poor controllability circuits are due to
Decoders
Clock generators
Circuits with feedback
355. The circuits with poor observability are:
A. ROM
B. PLA
C. Sequential circuits with long feedback loops
D. All of the mentioned
Answer: C
The circuits with poor observability are sequential circuits with long feedback loops.
356. A Large number of input vectors are used to set a particular node (1) or (0), to propagate an error at the node to output making the circuit low on:
A. Testability
B. Observability
C. Controllability
D. All of the mentioned
Answer: A
The circuit is said to be low on Testability if a large number of input vectors are used to set a particular node (1) or (0), to propagate an error at the node to output.
357. The divide and Conquer approach to large and complex circuits for testing is found in:
A. Partition and Mux Technique
B. Simplified automatic test pattern generation technique
C. Scan based technique
D. All of the mentioned
Answer: A
The divide and Conquer approach to large and complex circuits for testing is found in the partition and Mux technique.
358. LSSD stands for:
A. Linear system synchronous detection
B. Level sensitive system detection
C. Level sensitive scan design
D. Level sensitive scan detection
Answer: C
LSSD stands for Level sensitive scan design. The level-sensitive scan design technique was developed and pioneered by IBM and forms the basis for a structured approach to the design of testable circuits.
