300+ VLSI MCQ Quiz – Objective Question with Answer for VLSI

151. Sequential circuits are represented as

A. finite state machine
B. infinite state machine
C. finite synchronous circuit
D. infinite asynchronous circuit

Answer: A

Sequential circuits are represented as finite state machine and may be modeled as combinational logic.

 

152. Sequential circuit includes

A. delays
B. feedback
C. delays and feedback from the input to output
D. delays and feedback from output to input

Answer: D

A sequential circuit includes a set of delays and feedback from output to input and it is known as a finite state machine.

 

153. Which constitutes the test vectors in sequential circuits?

A. feedback variables
B. delay factors
C. test patterns
D. all input combinations

Answer: A

The ‘m’ feedback variables constitute the state vector and determine the maximum number of finite states which may be assumed by the circuit.

 

154. Outputs are functions of

A. present state
B. previous state
C. next state
D. present and next state

Answer: A

The next state and output are both functions of the present state and the independent inputs.

 

155. Which are the delay elements for the clocked system?

A. AND gates
B. OR gates
C. Flip-flops
D. Multiplexers

Answer: C

In clocked systems, the basic delay elements are flip-flops and in asynchronous circuits, the delays may be contributed by circuit propagation delays.

 

156. Which contributes to the necessary delay element?

A. flip-flops
B. circuit propagation elements
C. negative feedback path
D. shift registers

Answer: B

The circuit propagation delays contribute to the necessary delay elements. The delay in the feedback path may be non-existence.

 

157. In an OR gate, if A and B are two inputs and there is struck at 1 fault in B path, then the output will be

A. A
B. 0
C. 1
D. B’

Answer: C

In an OR gate, if struck at 1 fault is present in B path then the output will always be 1.

 

158. Iterative test generation method suits circuits with

A. no feedback loops
B. few feedback loops
C. more feedback loops
D. negative feedback loops only

Answer: B

The iterative test generation methods are best suited to logic with few feedback loops as in control logic for example.

 

159. Which method is very time-consuming?

A. D-algorithm
B. iterative test generation
C. pseudo exhaustive method
D. test generation pattern

Answer: B

The iterative test generation method is time-consuming for circuits of any complexity. It is necessary to describe the initial states of the circuit, which is also time-consuming.

 

160. In this technique, a simple fault manifests into multiple N faults.

A. true
B. false

Answer: A

The main problem in this iterative test generation technique is that a simple fault in the sequential machine is manifested as N multiple faults during the test.

 

161. In this iterative test generation method, sequential logic is

A. used in the same pattern
B. converted to test logic
C. converted to combinational logic
D. converted to asynchronous logic

Answer: C

In this iterative test generation method, the main approach of testing is sequential logic is converted into combinational logic by cutting the feedback lines, thus creating pseudo inputs and outputs.

 

162. For a NAND gate, struck-at 1 fault in the second input line cannot be detected if

A. Q is 1
B. Q is 0
C. Q changes from 1 to 0
D. Q changes from 0 to 1

Answer: B

In a NAND gate, a struck-at-1 fault in the second input line cannot be detected if the output Q is reset (Q=0) prior to applying the test sequence.

 

163. Practical guidelines for testability aim at

A. facilitating test generation
B. facilitating test application
C. avoiding timing problems
D. all of the mentioned

Answer: d

Practical guidelines for testability should aim to facilitate the test process in three main ways – facilitate test generation, facilitate test application and avoid timing problems.

 

164. When a node is difficult to access

A. sub-nodes are formed
B. internal pads are added
C. external pads are added
D. circuit is subdivided

Answer: b

When a node is difficult to access from primary input or output pads, then a very effective method is to add additional internal pads to access the desired point.

 

165. The additional pads are accessed using

A. probers
B. selectors
C. multiplexers
D. buffers

Answer: a

The additional pads which are added for the access of nodes can be accessed using probers.

 

166. Which provides links between blocks of a circuit?

A. combiners
B. wires
C. pads
D. nodes

Answer: d

A node provides the link between blocks of a circuit and the attributes provide the control of the blocks.

 

167. To improve controllability and observability ______ is used.

A. three pads
B. eight transistors
C. three pads and eight transistors
D. four pads and eight transistors

Answer: c

In a CMOS environment, three pads and eighth transistors are required to improve controllability and observability.

 

168. The addition of ______ improves the observability.

A. adders
B. multiplexers
C. multipliers
D. demultiplexer

Answer: d

The addition of demultiplexers also improves observability. This arrangement allows bypassing of blocks.

 

169. How to reduce test time?

A. by reducing multiplexers
B. by reducing adders
C. by dividing circuit into subcircuits
D. by using the whole circuit as a single system

Answer: c

Partitioning large circuits into smaller subcircuits is an effective way of reducing test generation complexity and test time.

 

170. Test generation effort for n gate circuit is proportional to

A. n
B. n2
C. n3
D. n2 and n3

Answer: d

Test generation effort for n gate general-purpose logic circuit is proportional to n2 and n3.

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