A. dividers
B. counters
C. RAM
D. all of the mentioned
Answer: d
Bypassing technique works well with counters, dividers, RAM, ROM, PLAs, sequential blocks, analog circuits, and internal clocks.
192. In the bypassing approach, the subsystem can be tested
A. exhaustively
B. pseudo-exhaustively
C. repeatedly
D. selectively
Answer: a
In the bypassing approach, subsystems can be tested exhaustively by controlling the multiplexers-based interconnections in the system.
193. The major difficulty in sequential circuit testing is in
A. determining output
B. determining an internal state
C. determining the external state
D. determining input combinations
Answer: B
The major difficulty in sequential circuit testing is in determining the internal state of the circuit.
194. The design technique helps in improving
A. controllability
B. observability
C. controllability and observability
D. overall performance
Answer: C
The design technique is directed at improving the controllability and observability of the internal states.
196. A sequential circuit contains combinational logic and storage elements in
A. feedback path
B. output node
C. input node
D. non-feedback path
Answer: A
A sequential circuit contains combinational logic and storage elements in the feedback path.
198. Storage elements in the scan design technique are reconfigured to form
A. RAM
B. shift registers
C. buffers
D. amplifiers
Answer: B
Storage elements in the scan design technique are reconfigured to form a shift register known as the scan path.
199. Storage elements used are
A. D flipflops
B. JK flipflops
C. RS flipflops
D. All of the mentioned
Answer: D
Storage elements are usually D, JK, and RS flipflop elements with the classical structure being modified by the addition of a two-way multiplexer on the data inputs.
200. The sequential circuit operates in _____ mode/modes of operation.
A. only one
B. two
C. three
D. four
Answer: B
The sequential circuit containing the scan paths has two modes of operation a normal and a test mode.
201. The efficiency of the test pattern generation is improved by
A. adding buffers
B. adding multipliers
C. partitioning
D. adding power dividers
Answer: C
The efficiency of the test pattern generation for the overall combinational logic circuit is improved by partitioning since its depth is reduced.
202. The scan path shift register is verified by
A. shifting in all zeroes first
B. shifting in all one first
C. adding all ones
D. adding all zeroes
Answer: B
Before applying test patterns, the scan path shift register is verified by shifting all ones then all zeroes.
203. In level-sensitive aspect, when an input change occurs, the response in
A. dependent on components
B. dependent on wiring delays
C. independent of wiring delays
D. independent of input combinations
Answer: C
In the level-sensitive aspect, when an input change occurs the response is independent of the component and wiring delays within the network.
204. In test mode, storage elements are connected as
A. parallel shift registers
B. serial shift register
C. combiners
D. buffers
Answer: B
In the test mode, storage elements are connected as a long serial shift register.
205. Which has more number of I/O pins?
A. lssd
B. partial scan
C. scan/set
D. random access scan
Answer: D
The random access scan method’s major disadvantage is that it has more number of I/O pins and no shift registers with flip-flops are used.
206. Scan/set method has no interruption to normal operation.
A. true
B. false
Answer: A
The scan/set method has separate shift registers and has no interruption to normal operation.
207. Which method has a high overhead cost?
A. lssd
B. partial scan
C. scan/set
D. random access scan
Answer: C
The scan/set method has a high overhead cost in terms of additional input/output pins.
208. The serial shift register is driven using
A. one over-lapping clock
B. two over-lapping clock
C. one non-over-lapping clock
D. two non-over-lapping clock
Answer: D
The serial shift register is driven using two non-over-lapping clocks which can be controlled by the primary inputs of the circuit.
209. Which is used to control the scan path movement?
A. clock signals
B. input signals
C. output signals
D. delay signals
Answer: A
Two clock signals are used to control the scan path movements through the shift register latches.
210. The circuit operation is independent of
A. rise time
B. fall time
C. propagation delays
D. all of the mentioned
Answer: D
The circuit operation is independent of dynamic characteristics of the logic elements like rising time, fall time, and propagation delays.