1. Microelectronic technology cannot be characterized by
a) minimum feature size
b) power dissipation
c) production cost
d) designing cost
Answer: d
Microelectronic technology can be characterized by minimum feature size, a number of gates on one chip, power dissipation, die size, production cost, etc, and not by design cost.
2. Which model is used for scaling?
a) constant electric scaling
b) constant voltage scaling
c) constant electric and voltage scaling
d) constant current model
Answer: c
The constant electric scaling model and constant voltage scaling model is used for scaling.
3. α is used for scaling
a) linear dimensions
b) vdd
c) oxide thickness
d) nonlinear
Answer: a
α is used as the scaling factor for linear dimensions whereas β is used for supply voltage Vdd, gate oxide thickness, etc.
4. For constant voltage model,
a) α = β
b) α = 1
c) α = 1/β
d) β = 1
Answer: d
For the constant voltage model, β = 1 and 1/β are chosen for the scaling for all voltages.
5. For constant electric field model,
a) β = α
b) α = 1
c) α = 1/β
d) β = 1
Answer: a
For constant voltage model, β = α.
6. Gate area can be given as
a) L/W
b) L * W
c) 2L/W
d) L/2W
Answer: b
Gate area Ag can be given as the product of length and the width of the channel.
7. Gate area is scaled by
a) α
b) 1/α
c) 1/α2
d) α2
Answer: c
Gate area is given as the product of the length and width of the channel and it can be scaled by 1/α2.
8. Gate capacitance per unit area is scaled by
a) α
b) 1
c) 1/β
d) β
Answer: d
Gate capacitance per unit area is scaled by β and this is given by €ox/D.
9. Parasitic capacitance is given by
a) Ax/d
b) Ax * d
c) d/Ax
d) Ax
Answer: a
Parasitic capacitance is given by Ax/d where Ax is the area of the depletion region and d is the depletion width
.
10. Parasitic capacitance is scaled by
a) β
b) 1/β
c) α
d) 1/α
Answer: d
Parasitic capacitance is scaled by 1/α because area is scaled by 1/α2 and d by 1/α. Thus (1/α2)/(1/α) we will get 1/α.
