1. The major difficulty in sequential circuit testing is in
A. determining output
B. determining an internal state
C. determining the external state
D. determining input combinations
2. The design technique helps in improving
A. controllability
B. observability
C. controllability and observability
D. overall performance
3. A sequential circuit contains combinational logic and storage elements in
A. feedback path
B. output node
C. input node
D. non-feedback path
4. Storage elements in the scan design technique are reconfigured to form
A. RAM
B. shift registers
C. buffers
D. amplifiers
5. Storage elements used are
A. D flipflops
B. JK flipflops
C. RS flipflops
D. All of the mentioned
6. The sequential circuit operates in _____ mode/modes of operation.
A. only one
B. two
C. three
D. four
7. The efficiency of the test pattern generation is improved by
A. adding buffers
B. adding multipliers
C. partitioning
D. adding power dividers
8. The scan path shift register is verified by
A. shifting in all zeroes first
B. shifting in all one first
C. adding all ones
D. adding all zeroes
9. In the level-sensitive aspect, when an input change occurs, the response in
A. dependent on components
B. dependent on wiring delays
C. independent of wiring delays
D. independent of input combinations
10. In test mode, storage elements are connected as
A. parallel shift registers
B. serial shift register
C. combiners
D. buffers