VLSI Sequential Logic Testing MCQ Quiz – Objective Question with Answer for Sequential Logic Testing in VLSI

1. Sequential circuits are represented as

A. finite state machine
B. infinite state machine
C. finite synchronous circuit
D. infinite asynchronous circuit

Answer: A

Sequential circuits are represented as finite state machine and may be modeled as combinational logic.


2. Sequential circuit includes

A. delays
B. feedback
C. delays and feedback from the input to output
D. delays and feedback from output to input

Answer: D

A sequential circuit includes a set of delays and feedback from output to input and it is known as a finite state machine.


3. Which constitutes the test vectors in sequential circuits?

A. feedback variables
B. delay factors
C. test patterns
D. all input combinations

Answer: A

The ‘m’ feedback variables constitute the state vector and determine the maximum number of finite states which may be assumed by the circuit.


4. Outputs are functions of

A. present state
B. previous state
C. next state
D. present and next state

Answer: A

The next state and output are both functions of the present state and the independent inputs.


5. Which are the delay elements for the clocked system?

A. AND gates
B. OR gates
C. Flip-flops
D. Multiplexers

Answer: C

In clocked systems, the basic delay elements are flip-flops and in asynchronous circuits, the delays may be contributed by circuit propagation delays.


6. Which contributes to the necessary delay element?

A. flip-flops
B. circuit propagation elements
C. negative feedback path
D. shift registers

Answer: B

The circuit propagation delays contribute to the necessary delay elements. The delay in the feedback path may be non-existence.


7. In an OR gate, if A and B are two inputs and there is struck at 1 fault in B path, then the output will be

A. A
B. 0
C. 1
D. B’

Answer: C

In an OR gate, if struck at 1 fault is present in B path then the output will always be 1.


8. Iterative test generation method suits circuits with

A. no feedback loops
B. few feedback loops
C. more feedback loops
D. negative feedback loops only

Answer: B

The iterative test generation methods are best suited to logic with few feedback loops as in control logic for example.


9. Which method is very time-consuming?

A. D-algorithm
B. iterative test generation
C. pseudo exhaustive method
D. test generation pattern

Answer: B

The iterative test generation method is time-consuming for circuits of any complexity. It is necessary to describe the initial states of the circuit, which is also time-consuming.


10. In this technique, a simple fault manifests into multiple N faults.

A. true
B. false

Answer: A

The main problem in this iterative test generation technique is that a simple fault in the sequential machine is manifested as N multiple faults during the test.

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