VLSI Sequential Logic Testing MCQ Quiz – Objective Question with Answer for Sequential Logic Testing in VLSI

11. In this iterative test generation method, sequential logic is

A. used in the same pattern
B. converted to test logic
C. converted to combinational logic
D. converted to asynchronous logic

Answer: C

In this iterative test generation method, the main approach of testing is sequential logic is converted into combinational logic by cutting the feedback lines, thus creating pseudo inputs and outputs.


12. For a NAND gate, struck-at 1 fault in the second input line cannot be detected if

A. Q is 1
B. Q is 0
C. Q changes from 1 to 0
D. Q changes from 0 to 1

Answer: B

In a NAND gate, a struck-at-1 fault in the second input line cannot be detected if the output Q is reset (Q=0) prior to applying the test sequence.


13. Practical guidelines for testability aim at

A. facilitating test generation
B. facilitating test application
C. avoiding timing problems
D. all of the mentioned

Answer: d

Practical guidelines for testability should aim to facilitate the test process in three main ways – facilitate test generation, facilitate test application and avoid timing problems.


14. When a node is difficult to access

A. sub-nodes are formed
B. internal pads are added
C. external pads are added
D. circuit is subdivided

Answer: b

When a node is difficult to access from primary input or output pads, then a very effective method is to add additional internal pads to access the desired point.


15. The additional pads are accessed using

A. probers
B. selectors
C. multiplexers
D. buffers

Answer: a

The additional pads which are added for the access of nodes can be accessed using probers.


16. Which provides links between blocks of a circuit?

A. combiners
B. wires
C. pads
D. nodes

Answer: d

A node provides the link between blocks of a circuit and the attributes provide the control of the blocks.


17. To improve controllability and observability ______ is used.

A. three pads
B. eight transistors
C. three pads and eight transistors
D. four pads and eight transistors

Answer: c

In a CMOS environment, three pads and eighth transistors are required to improve controllability and observability.


18. The addition of ______ improves the observability.

A. adders
B. multiplexers
C. multipliers
D. demultiplexer

Answer: d

The addition of demultiplexers also improves observability. This arrangement allows bypassing of blocks.


19. How to reduce test time?

A. by reducing multiplexers
B. by reducing adders
C. by dividing circuit into subcircuits
D. by using the whole circuit as a single system

Answer: c

Partitioning large circuits into smaller subcircuits is an effective way of reducing test generation complexity and test time.


20. Test generation effort for n gate circuit is proportional to

A. n
B. n2
C. n3
D. n2 and n3

Answer: d

Test generation effort for n gate general-purpose logic circuit is proportional to n2 and n3.

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