VLSI Simulator MCQ Quiz – Objective Question with Answer for VLSI Simulator

11. The charge carriers reach _________ scattering limited velocity before pinch-off.

A. maximum
B. minimum
C. less
D. equal

Answer: A

Velocity saturation occurs when the drain to source voltage of a short channel transistor exceeds a critical value, and the charge reaches its maximum scattering limited velocity before pinch-off.

 

12. Less current is available from

A. short channel transistor
B. large channel transistor
C. very large channel transistor
D. does not depend on channel transistor

Answer: A

Less current is available from a short channel transistor than from a long channel transistor with similar width to length ratio and processing.

 

13. Which can cope with large sections of layout?

A. circuit simulator
B. timing simulator
C. logic level simulator
D. functional simulator

Answer: C

The logic level simulator can cope with a large section of the layout at one time but the performance is assumed in terms of logic levels with no or little timing information.

 

14. Logic simulators can be replaced by simulators which operate at the transistor level.

A. true
B. false

Answer: B

Logic simulators may be replaced by simulators which operate at the register transfer level.

 

15. Circuit nodes cannot be probed for monitoring or excitation.

A. true
B. false

Answer: A

The entire surface of the chip other than the pads are sealed by cover glass layers and thus circuit nodes cannot be probed for monitoring and excitation.

 

16. The circuit should be tested at

A. design level
B. chip level
C. transistor level
D. switch level

Answer: B

Chip design mistakes can be very costly both in terms of time and money. The circuit should be tested at the chip level itself. Design for testability is essential for good design.

 

17. ______ of the area is dedicated for testability.

A. 20%
B. 10%
C. 30%
D. 25%

Answer: C

Design for testability is an essential process for good design. Thus the designers dedicate around 30% or more of the chip area for testing.

 

18. Partitioning into subsystems is done at

A. design stage
B. prototype stage
C. testing stage
D. fabrication stage

Answer: B

At the prototype stage, partitioning into subsystems are done to solve all the complex problem. Each of these subsystems is self-contained and independent.

 

19. In prototype testing, the circuits are

A. open circuited
B. short-circuited
C. tested as a whole circuit
D. programmed

Answer: A

The connections are made open-circuited so that one system can be divorced from another as a last resort in prototype testing.

 

20. The number of test vectors for exhaustive testing is calculated by

A. 2(m+n)
B. 2((m+n)/2)
C. 2(m-n)
D. 22(m+n)

Answer: A

The total number of test vectors for exhaustive testing is given by 2(m+n). For example, if m is 20 and n is 24, the resultant number of test vectors for exhaustive testing is 244.

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