A. transistor logic
B. switch logic
C. complementary logic
D. restoring logic
Answer: D
Gate logic is also called restoring logic. This is a logic circuitry designed so that even with an imperfect input pulse a standard output occurs at the exit of each successive logic gate.
12. Both NAND and NOR gates can be used in gate logic.
A. true
B. false
Answer: A
Both NAND and NOR gates can be used in gate logic along with CMOS and AND and OR logic can be used in switch logic.
13. The CMOS inverter has _____ power dissipation.
A. low
B. more
C. no
D. very less
Answer: C
The CMOS inverter has no static current and no power dissipation. The static charge remains until it is able to move away by means of electric discharge.
14. As the number of inputs increases, the NAND gate delay
A. increases
B. decreases
C. does not vary
D. exponentially decreases
Answer: A
As the number of inputs increases, the NAND gate delay also increases because computation considering or using each input additional time is needed.
15. NAND gate delay can be given as
A. Ʈint
B. Ʈint/n
C. n × Ʈint
D. 2n × Ʈint
Answer: C
NAND gate delay can be given as the product of a number of inputs n and the nMOS inverter delay Ʈint.
16. In the CMOS NAND gate, p transistors are connected in
A. series
B. parallel
C. cascade
D. random
Answer: B
In the CMOS NAND gate, p transistors are connected in parallel but once again the geometries may require thought when several inputs are required.
17. BiCMOS is used for ____ fan-out.
A. less
B. more
C. no
D. very less
Answer: B
BiCMOS NAND can be used when a large fan-out is necessary. Fan-out is a term that defines the maximum number of digital inputs that the output of a single logic gate can feed.
18. Which can handle high capacitance load?
A. NAND
B. nMOS NAND
C. CMOS NAND
D. BiCMOS NAND
Answer: D
BiCMOS NAND can handle high capacitance load. It is more complex and it can handle high capacitance loads such as in the I/O region of a chip.
19. Which gate is faster?
A. AND
B. NAND
C. NOR
D. OR
Answer: C
NOR gate is faster. NAND is more complex than NOR and thus NOR is faster and more efficient.
20. For a pseudo-nMOS design the impedance of pull up and pull down ratio is
A. 4:1
B. 1:4
C. 3:1
D. 1:3
Answer: C
For a pseudo-nMOS design, the ratio of Zp.u. and Zp.d. is 3:1.
Pseudo—NMOS logic uses only one PMOS device as a pull-up device for a multi- transistor N—Logic block.
Therefore, the required number of transistors for an N-input gate is an N+1 transistor.
