51. At narrowing or constriction point current density is ________
A. minimum
B. maximum
C. remains low after going to a high point
D. becomes high from low
Answer: B
At the narrowing or constriction point, the current density is at its highest. At these points, metal transported from the constricted regions becomes even more constricted and eventually may blow like a fuse.
52. During the relaxation effect, electron flow occurs in
A. short pulses
B. at a steady-state level
C. large pulses
D. very large pulses
Answer: A
During the relaxation effect, electron flow occurs in short pulses rather than at a steady-state level.
53. Line impedance is given by
A. (L/C)2
B. (C/L)2
C. (L/C)1/2
D. (C/L)1/2
Answer: C
The line impedance Zo is given by (L/C)1/2 where L and C are values per unit length of the bus.
54. IR drops brings ______ in noise margin.
A. increase
B. decrease
C. does not affect
D. stabilization
Answer: B
IR drops bring about deterioration in noise margins. Transient voltages induced in either Vdd or Vss rail may lead to noise margin problems.
55. In negative logic convention, the Boolean Logic [1] is equivalent to:
A. +VDD
B. 0 V
C. -VDD
D. None of the mentioned
Answer: B
In negative logic convention, the Boolean Logic [1] is equivalent to 0 V and Logic ‘0’ is equivalent to +VDD.
56. In positive logic convention, the true state is represented as:
A. 1
B. 0
C. -1
D. -0
Answer: A
In positive logic convention, the Boolean logic ‘1’ is known to be representing the true state.
In Positive Logic Convention the more positive potential is considered to represent true or logic 1, and the more negative potential is considered to represent false or logic 0.
57. In a CMOS logic circuit the n-MOS transistor acts as:
A. Load
B. Pull up network
C. Pull down the network
D. Not used in CMOS circuits
Answer: C
A static CMOS gate has an nMOS pull-down network to connect the output to 0 (GND.
Pulldown network provides a low resistance path to Gnd when output is logic ‘0’ and provides high resistance to Gnd otherwise.
58. In a CMOS logic circuit the p-MOS transistor acts as:
A. Pull down network
B. Pull up network
C. Load
D. Short to ground
Answer: B
A static CMOS gate has a pMOS pull-up network to connect the output to VDD (1).
The Pullup network provides a low resistance path to Vdd when output is logic ‘1’ and provides high resistance to Vdd otherwise.
59. In the CMOS logic circuit, the switching operation occurs because:
Both n-MOSFET and p-MOSFET turn OFF simultaneously for input ‘0’ and turn ON simultaneously for input ‘1’
Both n-MOSFET and p-MOSFET turn ON simultaneously for input ‘0’ and turns OFF simultaneously for input ‘1’
N-MOSFET transistor turns ON, and the p-MOSFET transistor turns OFF for input ‘1’ and the N-MOS transistor turns OFF, and the P-MOS transistor turns ON for input ‘0’
None of the mentioned
Answer: C
In the CMOS logic circuit, the switching operation occurs because the N-MOS transistor turns ON, and the P-MOS transistor turns OFF for input ‘1’
For Input 0 the N-MOS transistor turns OFF, and the P-MOS transistor turns ON.
The networks are arranged such that one is ON and the other OFF for any input pattern.
60. When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is:
A. 1 or Vdd or HIGH state
B. 0 or ground or LOW state
C. High impedance or floating(Z)
D. None of the mentioned
Answer: C
When both pull up and pull down transistors are OFF the high impedance for floating Z output state results.
