# VLSI testing and testability MCQ Quiz – Objective Question with Answer for VLSI testing and testability

1. Circuit nodes cannot be probed for monitoring or excitation.

A. true
B. false

The entire surface of the chip other than the pads are sealed by cover glass layers and thus circuit nodes cannot be probed for monitoring and excitation.

2. The circuit should be tested at

A. design level
B. chip level
C. transistor level
D. switch level

Chip design mistakes can be very costly both in terms of time and money. The circuit should be tested at chip level itself. Design for testability is essential for good design.

3. ______ of the area is dedicated for testability.

A. 20%
B. 10%
C. 30%
D. 25%

Design for testability is an essential process for good design. Thus the designers dedicate around 30% or more of the chip area for testing.

4. Partitioning into subsystems is done at

A. design stage
B. prototype stage
C. testing stage
D. fabrication stage

At the prototype stage, partitioning into subsystems are done to solve all the complex problem. Each of these subsystems is self-contained and independent.

5. In prototype testing, the circuits are

A. open circuited
B. short-circuited
C. tested as a whole circuit
D. programmed

The connections are made open-circuited so that one system can be divorced from another as a last resort in prototype testing.

6. The number of test vectors for exhaustive testing is calculated by

A. 2(m+n)
B. 2((m+n)/2)
C. 2(m-n)
D. 22(m+n)

The total number of test vectors for exhaustive testing is given by 2(m+n). For example, if m is 20 and n is 24, the resultant number of test vectors for exhaustive testing is 244.

7. After partitioning, the number of vectors is given by

A. 2(m+n)
B. 2((m+n)/2)
C. 2n+ 2m
D. 22(m+n)

If the system is partitioned for testing, exhaustive testing can be reduced to 2n + 2m a much more reasonable proportion.

8. What are the dominant faults in diffusion layers?

A. short circuit faults
B. open circuit faults
C. short and open circuit faults
D. power supply faults

In MOS circuits, short circuits and open circuits in the metal layer and short circuits in the diffusion layer are the dominant faults experienced.

9. Test pattern generation is assisted using

A. automatic test pattern generator
B. exhaustive pattern generator
C. repeated pattern generator
D. loop pattern generator

Test pattern generation is assisted using automatic test pattern generators but they are complicated to use properly and ATPG costs tend to rise rapidly with circuit size.

10. _____ of faults are easier to detect.

A. 50%
B. 60%
C. 70%
D. 80%