Cache Memory Writing Scheme MCQ Quiz – Objective Question with Answer for Writing Scheme of Cache Memory

The problem of cache coherency lead to the formation of two standard mechanisms called MESI and MEI protocol. MC88100 has a MESI protocol and MC68040 uses an MEI protocol.

The MESI protocol is also known as the Illinois protocol because of its formation at the University of Illinois.

The MESI protocol supports a shared state which is a formal mechanism for controlling the cache coherency by using the bus snooping techniques. MESI refers to the states that cached data can access. In the MESI protocol, multiple processors can cache shared data.

MEI protocol is less complex and easy to implement. It does not allow a shared state for the cache.

MPC601 uses a MESI protocol, that is they have a shared state for data accessing in the cache. It can reduce the cache coherency but the cache coherency is processor-specific. So different processors have different cache coherency implementations.

The burst interfacing has special memory interfaces which include special address generation and data latches that help in the high performance of the processors. It takes the advantages of both the nibble mode memories and paging.

The burst interfaces use the burst fill technique in which the processor will access four words in succession, which fetches the complete cache line or written out to the memory.

The speed of the memory can be improved by the page mode or the static column memory which offers faster access in a single cycle.

The burst interfaces reduce the clock cycles. For fetching four words with a three-clock memory, it will take 12 clock cycles but in the burst interface, it will only take five clocks to access the data.

In the burst interface, the first access of the memory address requires two clock cycles and a single cycle for the remaining memory address.