Cache Memory Writing Scheme MCQ Quiz – Objective Question with Answer for Writing Scheme of Cache Memory

In the burst interface, the address is supplied only for the first access and not for the remaining accesses. External logic is required for the additional addresses for the memory interface.

The burst interfacing uses unequal timing. It takes two clocks for the first access and only one for the remaining accesses which makes it unequal timing.

The burst interfaced is associated with the SRAM and for the efficiency of the SRAM, it uses a synchronous memory on-chip latches to reduce the gate delays.

The burst interface is associated with the static RAM.

MC68040 is developed by Motorola and uses wrap-around burst interfacing. MC68030 is also developed by Motorola but it uses a linear line fill burst. HyperBus can switch to both linear and wrap-around bursts. US 5729504 A uses a linear burst fill.

MCM62940 protocol is developed by Motorola, whereas Slave interfaces, and AXI slave interfaces are for ARM. Avalon is developed by Altera.

MC68030 uses a linear burst fill whereas MC68040, US 74707 B2 uses wrap-around burst interfacing. HyperBus can switch to both linear and wrap-around interfacing.

The MCM62486 has an on-chip counter that matches the Intel 80486 and is developed by Motorola.

The MCM62940 and MCM62486 are the specific protocols developed by Motorola, in which the MCM62940 has an on-chip counter which matches the wrap-around burst interfacing of the MC68040.