Archives: Questions
Answer & Solution
Answer:Option 3
Solution:
- The PCI BUS has 4 interrupt request lines.
- By writing into a device configuration register, the software instructs the device as to which of these lines it can use to request an interrupt.
- If a device requires initialization, the initialization code is stored in a ROM in the device interface.
- (This is a different ROM from that used in the configuration process.) The PCI software reads this code and executes it to perform the required initialization.
Answer & Solution
Answer:Option 2
Solution:
- The device connected to the BUS is given an address of 64 bits.
- The PCI bus clock is 33 MHz. The address bus width is 32-bits (4GB memory address space), although PCI optionally supports 64-bit address buses.
- The data bus width is implemented as either 32-bits or 64-bits depending on bus performance requirement.
- Each of the devices connected to the BUS will be allocated an address during the initialization phase.
Answer & Solution
Answer:Option 1
Solution:
- A complete transfer operation over the BUS, involving the address and a burst of data is called a Transaction.
- Consider a bus transaction in which the processor reads four 32-bit words from the memory.
- In this case, the initiator is the processor and the target is the memory.
- A complete transfer operation on the bus, involving an address and a burst of data, is called a transaction.
- Individual word transfers within a transaction are called phases.
- A clock signal provides the timing reference used to coordinate different phases of a transaction.
Answer & Solution
Answer:Option 2
Solution:
- Signals whose names end in # are asserted in the low voltage state.
- The # symbol at the end of a signal name indicates that the active, or asserted, slate occurs when the signal is at a low voltage.
- When a # symbol is not present after the signal name, the signal is active. or asserted, at the high voltage level.
- Square brackets around a signal name indicate that the signal is defined only at RESET.
Answer & Solution
Answer:Option 1
Solution:
- The master is also called as Initiator in PCI terminology.
- In PCI terminology, the master and slave are called the initiator and target, respectively.
- All transactions on the bus are between an initiator and a target. The PCI bus uses a centralized arbiter with independent request lines.
- The initiator, or bus master, is the device that initiates a transfer.
- The terms bus master and initiator can be used interchangeably and frequently are in the PCI specification.
- The target is the device currently addressed by the initiator for the purpose of performing a data transfer.
- PCI initiator and target devices are commonly referred to as PCI-compliant agents in the spec.
Answer & Solution
Answer:Option 1
Solution:
- When transferring data over the PCI BUS, the slave hold the address until the completion of the transfer to the slave.
- A PCI add-in card can either be a slave or a bus master.
- Peripherals tend to be bus slaves logical devices capable only of responding to a transfer request from a bus master device.
- The address is stored by the slave in a buffer and hence it is not required by the master to hold it.
Answer & Solution
Answer:Option 3
Solution:
- PCI bridge provides a separate physical connection to the memory.
- A PCI bridge chip is a device that connects a PCI bus to either another PCI bus or a bus of a different standard.
- PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses.
- Transactions occur between masters on one PCI bus and targets on another PCI bus, and the PCI2250 allows bridged transactions to occur concurrently on both buses.
Answer & Solution
Answer:Option 1
Solution:
- Configuration address space gives the PCI its plug and plays capability.
- The PCI configuration space consists of up to six 32-bit base address registers for each device. These registers provide both size and data type information.
- System firmware assigns base addresses in the PCI address domain to these registers.
- Each addressable region can be either memory or I/O space.
- The configuration address space is used to store the details of the connected device.
Answer & Solution
Answer:Option 4
Solution:
- The PCI BUS supports I/O, Memory and Configuration address space/s.
- The bus transactions to memory, I/O, and configuration address spaces imply that the PCI bus master accesses data within a target by providing a specific address.
- These bus transactions are memory read and write, I/O read and write, and configuration read and write.
- The term “memory mad transactions” relative to PCI includes memory read, Memory Read Multiple (MRM).
- The PCI BUS is mainly built to provide a wide range of connectivity for devices.
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