41. How an alternate set of the register can be identified in Z80?
A. ‘Suffix
B. ‘Prefix
C. ,suffix
D. ,prefix
Answer: A
In order to identify the main register and alternate register ‘ is used in the suffix.
42. What is the purpose of the memory refresh register of Z80?
A. To control on-chip DRAM
B. To control on-chip SRAM
C. To control ROM
D. To clear cache
Answer: A
In addition to the general-purpose registers, a stack pointer, program counter, and two index registers are included in Z80. It was also used in many embedded designs because of its high-quality performance and for its in-built refresh circuitry for DRAMs.
43. What is the clock frequency of Z80?
A. 6 MHz
B. 8 MHz
C. 4 MHz
D. 2 MHz
Answer: C
It is the maximum clock frequency or runs a time of the processor.
44. Which are the two additional registers of Z80?
A. Interrupt and NMI
B. NMI and PSW
C. Interrupt vector and memory refresh
D. NMI and memory refresh
Answer: C
The Interrupt Vector(IV) register is used in interrupt handling. Mode 2 is used to point to the required software routine to process the interrupt. In mode 1, the interrupt vector is supplied via the external data bus.
45. By which instruction does the switching of registers take place?
A. Instruction opcodes
B. AXX instruction
C. EXX instruction
D. Register instruction
Answer: C
Only one set of registers can be used at one time and the switching of registers and data transfer is performed by the EXX instruction.
46. Which of the following can be a paired set of 16-bit registers?
A. CD
B. HL
C. AB
D. EH
Answer: B
Registers B, C, D, E, H, and L are 8-bit general-purpose registers that can be concatenated to produce 16 registers known as BC, DE, and HL.
47. Which signal is used to differentiate the access from a normal memory cycle?
A. HALT
B. RESET
C. MREQ
D. IORQ
Answer: D
The IORQ signal is used to differentiate the access from a normal memory cycle. These input/output accesses are similar from a hardware perspective to a memory cycle but only occur when an input/output port instruction is executed.
48. What is done in mode1 of Z80?
A. Interrupt vector is supplied via the external bus
B. Interrupt vector is supplied via the peripherals
C. NMI gets started
D. Interrupt gets acknowledged by peripheral
Answer: A
In mode 1, the interrupt vector is supplied via the external data bus. The memory refresh register is used to control the on-chip DRAM refresh circuitry.
49. What does the m1 signal in Z80 describes?
A. I/O operation status
B. Memory refresh output
C. Output pulse on instruction fetch cycle
D. Interrupt request input
Answer: C
It is a signal which describes the output pulse on the instruction fetch cycle. Interrupt request input, input/output operation status, and memory refresh output are the other signals in Z80 for various operations.
50. Which memory storage is widely used in PCs and Embedded Systems?
a) EEPROM
b) Flash memory
c) SRAM
d) DRAM
Answer: d
DRAM is used in PCs and Embedded systems because of its low cost. SRAM, flash memory, and EEPROM are more costly than DRAM.
