Phase Locked Loop MCQ [Free PDF] - Objective Question Answer for Phase Locked Loop Quiz

61. Filter used in switching regulators are also as called

A. DC – AC transformers
B. AC – DC transformers
C. DC transformer
D. AC transformer

Answer: C

The filter converts the pulse waveform from the output of the switch into a dc voltage. Since this switching mechanism allows a conversion similar to transformers, the switching regulator is often referred to as DC transformers.

62. Which of the following is considered to be the most important components of the switching regulator?

A. RC or RLC filter
B. RL or RLC filter
C. ORC or RL filter
D. RC, RLC or RL filter

Answer: B

RL or RLC filter is the most important component of the switching regulator because several areas are affected by the choke of the inductor including energy storage for the regulator’s output ripple, transient, response etc.

63. Which are the most commonly used low voltage switching regulators?

A. Powdered Permalloy toroids
B. Fermite EI, U and toroid cores
C. Silicon steel EI butt stacks
D. None of the mentioned

Answer: C

The silicon steel EI butt stack exhibits high permeability high flux density and ease of construction and mounting therefore, it is most commonly used in low voltage switching regulators.

64. Find the value of R_sc, L, and C_o for a µA7840 switching regulator to provide +5 v at 3A, using the following specifications: t_off= 24µs, ripple voltage = 400mA, and t_on=26µs.

A. R_sc = 55 mΩ , L = 25µH & C_o = 750µF
B. R_sc = 550 mΩ , L = 25µH & C_o = 75µF
C. R_sc = 650 mΩ , L = 25µH & C_o = 65µF
D. R_sc = 720 mΩ , L = 25µH & C_o = 250µF

Answer: A

Peak current

I_pk= 400mA× 1.5 (since I_pk = 1.5 A for peak current)

∴ R_sc = 0.33ohm/I_pk

= 0.33ohm/6 = 0.055ohm.

=> L= [(V_o +V_p) / I _pk]×t_off

=[(5+1.25) /6 ]× 24×10^-6 =25µH.

=> C_o = [I_pk (T_on +T_off)]/[8×V_ripple]

∵T = [t_on + t_off] = 26µs + 24µs = 50µs

=> C_o = [ (6×50µs)]/(8×50mA. = 7.5×10^-4 = 750µF.

65. Calculate the efficiency of the step-down switching regulator has given the input voltage V_in= 13.5v and output voltage =6v. Assume the saturating Voltage V_s=1.1v and the forward voltage drop V_d = 1.257v

A. η = 75%
B. η = 48.5%
C. η = 63.9%
D. η = 80.5%

Answer: D

Efficiency of the step down switching regulator

η = {[(V_in-V_s+V_d)]/ [V_in]}×(V_o) / [(V_o+V_d)]

= {[(13.5v-1.1v+1.257v)/13.5v]} ×[(6/(6 ×1.257)]

=> Efficiency of switching regulator, η = (1.012×0.7955)×100 =

0.8051×100 = 80.5%.

66. Match the characteristics of various switching regulators.

Switching regulator	Characteristics
1. Inverting	(i) [t_on / t_off ] = [ V_o + V_d] / [V_in -V_s -V_d]; R_sc = ( 0.33/ I_pk)
2. step down	(ii) [t_on / t_off ] = [ V_o + V_d -V_in] / [V_in-V_s] ; R_sc = ( 0.33/ I_pk)
3. step up	(iii) [t_on / t_off ] = [ Modulus V_o +V_d] / (V_in-V_s); R_sc = ( 0.33/ I_pk

A. 1- iii , 2- i , 3- ii
B. 1- i , 2- ii , 3- iii
C. 1- iii , 2- ii , 3- i
D. 1- iii , 2- ii , 3- i

Answer: B

Characteristics and design formula for step up, step down and converting mode of switching regulator.

Switching regulator	Characteristics
1. Inverting	(i) [t_on / t_off ] = [ V_o + V_d] / [V_in -V_s -V_d]; R_sc = ( 0.33/ I_pk)
2. step down	(ii) [t_on / t_off ] = [ V_o + V_d -V_in] / [V_in-V_s] ; R_sc = ( 0.33/ I_pk)
3. step up	(iii) [t_on / t_off ] = [ Modulus V_o +V_d] / (V_in-V_s); R_sc = ( 0.33/ I_pk

67. What is the conversion ratio of the phase detector in 565 PLL?

A. 0.14
B. 0.35
C. 0.4458
D. 0.7

Answer: C

The conversion ratio of the phase detector of

565 PLL (Monolithic PLL) K_φ = 1.4/π = 0.4458.

68. Given f_o = 1.2kHz and V = 13v, find the lock-in range of the monolithic Phase-Locked Loop.

A. ±575Hz
B. ±720Hz
C. ±150Hz
D. ±1kHz

Answer: B

The lock-in range of monolithic PLL,

△f_L = ±(7.8×f_o)/V

= ±(7.8×1.2kHz)/13 = ±720Hz.

69. A monolithic phase detector is preferred for critical applications as it is:

A. Independent of variation in amplitude
B. Independent of variation in the duty cycle of the input waveform
C. Independent of variation in response time
D. Both 1 and 2

Answer: D

Monolithic phase detectors are not sensitive to harmonics of the input signal and changes in the duty cycle of input and output frequency.

70. Determine the capture range of IC PLL 565 for a lock-in range of ± 1kHz.

A. △FC = ±31.453Hz
B. △f_c = ±66.505Hz
C. △f_c = ±87.653Hz
D. None of the mentioned

Answer: B

The capture range is

△f_c = ±[△f_L/ (2π×3.6×10³×C]^0.5

= ±[1kHz/(2π×3.6×kΩ×10µF)]^0.5

= ±[1kHz/226.08×^-6]^0.5 = [4423]^0.5 = ±66.505Hz.

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