The final design of the RISC concept is called the RISC 1 which was published by ACM ISCA. It possesses 44500 transistors which can implement 31 instructions.
92. How many registers does the RISC 1 model have?
A. 68
B. 58
C. 78
D. 88
Answer: C
The RISC 1 model has 78 registers of size 32 bits.
93. Which of the architectures are made to speed up the processor?
A. CISC
B. RISC
C. program stored
D. von Neumann
Answer: B
RISC architecture is made for speeding up the processor with limited execution time whereas CISC architecture is mainly for code efficiency.
94. How did 8086 pass its control to 8087?
A. BUSY instruction
B. ESCAPE instruction
C. CONTROL instruction
D. fetch 8087
Answer: B
When 8086 comes across any floating-point arithmetic operations, it executes ESCAPE instruction code in order to pass the control of bus and instruction op-code to 8087.
95. Which of the following processor supports MMX instructions?
A. 8080
B. 80486
C. Intel Pentium
D. 80386
Answer: C
MMX instructions or multimedia extensions were introduced in Pentium processors to provide support for multimedia software running on a PC.
96. Which of the following processors has a speculative execution?
A. 80486
B. P1
C. Intel Pentium
D. Pentium pro
Answer: D
Speculative execution is executed speculatively that is, following the predicted branch paths in the code until the true path is determined. If the processor executes correctly, then the performance is gained, if not, the results are discarded and the processor continues to execute until the correct path is identified.
97. How many bit accumulators does DSP56000 have?
A. 28
B. 56
C. 112
D. 14
Answer: B
The ALU of DSP56000 has two 56-bit accumulators A and B each of which has a small register with it.
98. How many additional registers does DSP56000 have?
A. 2
B. 4
C. 6
D. 8
Answer: B
In addition to the six registers of DSP56000, it has four 24-bit registers X1, X0, Y1, Y0 which can be concatenated to form 48-bit registers X and Y.
99. What does the MAC instruction of DSP56000 stand for?
A. multiply accumulator
B. multiple access
C. multiple accounting
D. multiply accumulator counter
Answer: A
When MAC instruction is executed, the two of the 24-bit additional registers are multiplied together and then added or subtracted from A and B. It takes place in a single machine cycle of 75ns at 27MHz.
100. What does SPARC stand for?
A. scalable processor architecture
B. speculating architecture
C. speculating processor
D. scaling Pentium architecture
Answer: A
SPARC was designed for optimizing compilers and easily pipelined hardware implementations and it can license by anyone that is, having a nonproprietary architecture that is used to develop various microprocessors.
