A. single-phase overlapping clock signal
B. single-phase non-overlapping clock signal
C. two-phase overlapping clock signal
D. two-phase non-overlapping clock signal
Answer: D
The two-phase non-overlapping clock signal is easily available and works better and more effectively and this clock will be used throughout the storage system.
2. Clock signal Φ2 is to
A. write data
B. read data
C. refresh data
D. store data
Answer: C
Bits or data written into storage elements may be assumed to be settled before the immediately following signal Φ2 refreshes stored data where appropriate.
3. Bits of data may be read from
A. before Φ1
B. after Φ1
C. before Φ2
D. after Φ2
Answer: B
Bits of data may be read from storage elements on the next of Φ1 clock signal that is read signals RD are Anded with Φ1.
4. Factors for assessment of storage elements are
A. volatility
B. non-volatility
C. number of bits
D. data repeatability
Answer: A
Some of the comparative assessment factors for storage elements are area requirement, estimated dissipation per bit stored, and volatility.
5. Which occupies a lesser area?
A. nMOS
B. pMOS
C. CMOS
D. BiCMOS
Answer: A
nMOS design with buried contacts needs a lesser area than CMOS design and this can be estimated by calculating the space stored by each bit in the register cell.
6. In which MOS design, dissipation is less?
A. nMOS
B. pMOS
C. CMOS
D. BiCMOS
Answer: C
In CMOS design, static dissipation is very small since only the switching dissipation will be significant, particularly at high speeds.
7. The impedance of the pull-down transistor in nMOS can be given as
A. 2Rs
B. 4Rs
C. 1/2 Rs
D. 1/4 Rs
Answer: C
Each inverter stage has an 8:1 ratio and in the nMOS register cell, at least one inverter should always be on and Zp.u. is given as 4Rs, and Zp.d. is given as 1/2Rs.
8. Data storage time is
A. 1 millisecond
B. 1 second
C. 1 minute
D. 10 seconds
Answer: A
Data is stored by the charge on the gate capacitance of each inverter stage, so that data storage time is limited to 1 msec or less.
9. A bit is read at T1 when
A. RD is low, WR is low
B. RD is high, WR is low
C. RD is low, WR is high
D. RD is high, WR is high
Answer: C
With RD control line low, a bit can be read through clock period T1 when WR is made high. After reading the bit WR is made low.
10. A bit can be stored when
A. RD is low, WR is low
B. RD is high, WR is low
C. RD is low, WR is high
D. RD is high, WR is high
Answer: A
A bit value is stored for some time by Cg of time period T2 while both RD and WR are made low.
11. Current flows only when
A. RD is low
B. RD is high
C. RD raises exponentially high
D. RD comes exponentially down
Answer: B
Current flows only when RD is high and 1 is stored. Thus static dissipating is nil.
12. Overhead bits are used for sensing.
A. true
B. false
Answer: A
Overhead bits are used for sensing. Some amount of overhead bits is used in the one-transistor dynamic memory cell.
In data transmission and telecommunication, overhead bits are non-data bits necessary for transmission (usually as part of headers, checksums, and such).
13. Reading a cell is a _______ operation.
A. constructive
B. destructive
C. semi constructive
D. semi destructive
Answer: B
Reading a cell is a destructive operation and the stored bit must be rewritten every time it is read.
A read operation inherently erases the data that was read, requiring it to be immediately written back to the storage medium to prevent loss of data.
14. RAM is a _____ cell.
A. dynamic
B. partially dynamic
C. static
D. pseudo-static
Answer: D
RAM is a pseudo-static cell. It stores data indefinitely and refreshing is not necessary.
Pseudo static RAM cell is built using two inverters and data can be stored in these two inverters by connecting it in parallel and using feedback.
15. Pseudo static RAM cell is built using
A. one inverter
B. two inverters
C. three inverters
D. four inverters
Answer: B
Pseudo static RAM cell is built using two inverters and data can be stored in these two inverters by connecting it in parallel and using feedback.
16. Cells must be non-stackable in RAM storage cell.
A. true
B. false
Answer: B
Cells must be stackable, both side by side and from top to bottom. This must be carefully considered when the layout is made.
17. Which cell is non-volatile?
A. one-transistor dynamic cell
B. two-transistor dynamic cell
C. four transistor dynamic cell
D. pseudo static RAM cell
Answer: D
Pseudo-static RAM cell is a non-volatile cell. It is used for long time storage. Non-volatile memory is also called long-term memory.
18. In RAM arrays, the transistor is of
A. minimum size
B. maximum size
C. of any size
D. size doesn’t play a role
Answer: A
In RAM arrays, the transistor is of minimum size and thus it is incapable of sinking large charges quickly.
19. Which implementation is slower?
A. NAND gate
B. NOR gate
C. AND gate
D. OR gate
Answer: B
NOR gate implementation is slower even though both NAND and NOR gate implementation is suitable for CMOS.
20. FOR nMOS which implementation is not suitable?
A. NAND gate
B. NOR gate
C. AND gate
D. OR gate
Answer: A
In nMOS, NAND gate implementation is impractical because of the large number of gates requiring three or more inputs.
21. Realization of JK flipflop is based on
A. n-pass transistor
B. p-pass transistor
C. CMOS
D. BiCMOS
Answer: A
The realization of the JK flip flop is based on the n-pass transistor and on inverters only.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level “1”.
22. Static RAM uses _________ transistors.
A. four
B. five
C. six
D. seven
Answer: C
Static RAM uses six transistors. In this RAM cell, read and write operations use the same port.
23. Which method is used to determine structural defects?
A. deterministic test pattern
B. algorithmic test pattern
C. random test pattern
D. exhaustive test pattern
Answer: A
Deterministic test patterns are used to detect specific faults or structural faults for a circuit under test.
24. Which is known as the stored test pattern method?
A. deterministic test pattern
B. algorithmic test pattern
C. random test pattern
D. exhaustive test pattern
Answer: A
The deterministic test pattern method is also known as the stored test pattern method in the context of BIST applications.
25. Which method uses a finite state machine for developing the test pattern?
A. deterministic test pattern
B. algorithmic test pattern
C. random test pattern
D. exhaustive test pattern
Answer: B
The algorithmic test pattern method uses the hardware finite state machine for generating algorithmic test vectors for the circuit under test.
26. A n-bit counter produces ______ number of total input combinations.
A. 2(n-1)
B. 2(n+1)
C. 2n
D. 2n
Answer: C
An n-bit counter produces a total of 2n number of all possible input combinations for testing the circuit under test and it is called an exhaustive test pattern method.
27. Exhaustive test pattern determines
A. gate-level faults
B. logic level faults
C. functional faults
D. structural faults
Answer: A
The exhaustive test pattern method detects all gate level struck-at fault and also bridging fault.
Exhaustive testing is the testing where we execute a single test case for multiple test data.
It means if we are using a single test case for different products or modules under manual testing.
28. Exhaustive test pattern also detects delay faults.
A. true
B. false
Answer: B
The exhaustive test pattern method does not detect all transistor-level faults or delay faults since those faults need specific ordering.
29. Which is not suitable for circuits having large N values?
A. exhaustive test pattern method
B. pseudo-exhaustive test pattern method
C. random test pattern method
D. deterministic test pattern method
Answer: A
The exhaustive test pattern method is not suitable for circuits having large N values since there is a limit for fault coverage.
30. Which method needs fault simulation?
A. exhaustive test pattern method
B. pseudo-exhaustive test pattern method
C. random test pattern method
D. deterministic test pattern method
Answer: A
The exhaustive test pattern method needs fault simulation for determining fault coverage whereas the pseudo-exhaustive test pattern method does not need fault simulation.
