41. The relation between threshold voltage and Noise Margin is:
A. Vth = sqrt(Noise Margin)
B. Vth = NMH – NML
C. Vth = (NMH+NML)/2
D. None of the mentioned
42. The Lower Noise Margin is given by:
A. VOL – VIL
B. VIL – VOL
C. VIL ~ VOL(Difference between VIL and VOL, depends on which one is greater)
D. All of the Mentioned
43. The Higher Noise Margin is given by:
A. VOH – VIH
B. VIH – VOH
C. VIH ~ VOH(Difference between VIH and VOH, depends on which one is greater)
D. All of the mentioned
44. The Uncertain or transition region is between:
A. VIH and VOH
B. VIL and VOL
C. VIH and VIL
D. VOH and VOL
45. The noise immunity _________ with noise margin.
A. Decreases
B. Increases
C. Constant
D. None of the Mentioned
46. If VIL of the 2nd gate is higher than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as:
A. Logic input 1
B. Uncertain
C. Logic input 0
D. None of the mentioned
47. If VIL of the 2nd gate is lower than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as:
A. Logic input 1
B. Uncertain
C. Logic input 0
D. None of the mentioned
48. Input Voltage between VIL and VOL is considered as:
A. Logic Input 1
B. Logic Input 0
C. Uncertain
D. None of the mentioned
49. If VIH of the 2nd gate is higher than VOH of the 1st gate, then logic output 0 from the 1st gate is considered as:
A. Logic input 1
B. Uncertain
C. Logic input 0
D. None of the mentioned
50. Noise margin of CMOS is:
A. Better than TTL and ECL
B. Less than TTL and ECL
C. Equal to TTL and ECL
D. None of the Mentioned