11. What does the MAC instruction of DSP56000 stand for?
A. multiply accumulator
B. multiple access
C. multiple accounting
D. multiply accumulator counter
Answer: A
When MAC instruction is executed, the two of the 24-bit additional registers are multiplied together and then added or subtracted from A and B. It takes place in a single machine cycle of 75ns at 27MHz.
12. What does SPARC stand for?
A. scalable processor architecture
B. speculating architecture
C. speculating processor
D. scaling Pentium architecture
Answer: A
SPARC was designed for optimizing compilers and easily pipelined hardware implementations and it can license by anyone that is, having a nonproprietary architecture that is used to develop various microprocessors.
13. How many bits does SPARC have?
A. 8
B. 16
C. 32
D. 64
Answer: C
It is a 32-bit RISC architecture having a 32-bit wide register bank.
14. Which company developed SPARC?
A. intel
B. IBM
C. Motorola
D. sun microsystem
Answer: D
SPARC is developed by Sun Microsystem but different manufacturers from other companies like Intel, Texas worked on it.
15. What improves the context switching and parameter passing?
A. register to window
B. large register
C. stack register
D. program counter
Answer: A
SPARC follows the Berkeley architecture model and uses register windowing in order to improve the context switching and parameter passing. It also supports superscalar operations.
16. How many external interrupts does the SPARC processor support?
A. 5
B. 10
C. 15
D. 20
Answer: C
SPARC processor provides 15 external interrupts which are generated by the interrupt lines IRL0-IRL3.
17. Which level is an in-built nonmaskable interrupt in the SPARC processor?
A. 15
B. 14
C. 13
D. 12
Answer: A
Level 15 of the SPARC processor is assigned to be a non-maskable interrupt and the remaining 14 levels are unmasked and if necessary they can be made maskable.
18. How many instructions does the SPARC processor have?
A. 16
B. 32
C. 64
D. 128
Answer: C
The instruction set of the SPARC processor has 64 instructions which can be accessed by load and store operation with a RISC architecture.
19. What is generated by an external interrupt in SPARC?
A. internal trap
B. external trap
C. memory trap
D. interfaced trap
Answer: A
In SPARC when an external interrupt is generated, an internal trap is created in the trap base register in which the current and next instructions are saved, the pipeline gets flushed and the processor turns into a supervisor mode.
20. When an external interrupt is generated, what type of mode does the processor support?
A. real mode
B. virtual mode
C. protected mode
D. supervisor mode
Answer: D
In SPARC when an external interrupt is called, it creates an internal trap in which the current and next instructions get saved and the mode of the processor switches to supervisor mode.
