The FTA is Fault tree analysis which is a top-down method of analyzing risks. It starts with damage and comes up with the reasons for the damage. The analysis is done graphically by using gates.

2. What is FTA?

a) free tree analysis
b) fault tree analysis
c) fault top analysis
d) free top analysis

Answer: b

The FTA is also known as the Fault tree analysis which is a top-down method of analyzing risks. The analysis starts with damage and comes up with the reasons for the damage. The analysis can be checked graphically by using gates.

3. Which gate is used in the geometrical representation, if a single event causes hazards?

a) AND
b) NOT
c) NAND
d) OR

Answer: d

The fault tree analysis is done graphically by using gates mainly AND gates and OR gates. The OR gate is used to represent a single event that is hazardous. Similarly, AND gates are used in the graphical representation if several events cause hazards.

4. Which analysis uses the graphical representation of hazards?

a) Power model
b) FTA
c) FMEA
d) First power model

Answer: b

The FTA is done graphically by using gates mainly AND gates and OR gates. The OR gate is used to represent a single event that is hazardous.

5. Which gate is used in the graphical representation, if several events cause a hazard?

a) OR
b) NOT
c) AND
d) NAND

Answer: c

The fault tree analysis is done graphically by using gates. The main gates used are AND gates and OR gates. The AND gates are used in the graphical representation if several events cause hazards.

6. What is FMEA?

a) fast mode and effect analysis
b) front mode and effect analysis
c) false mode and effect analysis
d) failure mode and effect analysis

Answer: d

The FMEA is the failure mode and the effect analysis, in which the analysis starts at the components and tries to estimate their reliability.

7. Which of the following can compute the exact number of clock cycles required to run an application?

a) layout model
b) coarse-grained model
c) fine-grained model
d) register-transaction model

Answer: c

The fine-grained model has the cycle-true instruction set simulation. In this modeling, it is possible to compute the exact number of clock cycles that are required to run an application.

8. Which model is capable of reflecting the bidirectional transfer of information?

a) switch-level model
b) gate level
c) layout model
d) circuit-level model

Answer: a

The switch model can be used in the simulation of the transistors since the transistor is the very basic component of a switch. It is capable of reflecting bidirectional transferring of the information.

9. What is meant by FOL?

a) free order logic
b) fast order logic
c) false order logic
d) first-order logic

Answer: d

Many formal verification techniques are used and these are classified based on the logic employed. The techniques are propositional logic, first-order logic, and higher-order logic. The FOL is the abbreviated form of the first-order logic which includes the quantification.

10. What is HOL?

a) higher-order logic
b) higher-order last
c) highly organized logic
d) higher-order less

Answer: a

The formal verification techniques are classified based on the logic employed. The techniques are propositional logic, first-order logic, and higher-order logic. The HOL is the abbreviation of the higher-order logic in which the proofs are automated and manually done with some proof support.