11. What are the basic elements required for cache operation?
A. memory array, multivibrator, counter
B. memory array, comparator, counter
C. memory array, trigger circuit, a comparator
D. memory array, comparator, CPU
Answer: B
The cache memory operation is based on the address tag, that is, the processor generates the address which is provided to the cache, and this cache stores its data with an address tag. The tag is compared with the address, if they did not match, the next tag is checked. If they match, a cache hit occurs, and the data is passed to the processor. So the basic elements required are a memory array, comparator, and a counter.
12. How many divisions are possible in the cache memory based on the tag or index address?
A. 3
B. 2
C. 4
D. 5
Answer: C
There are four classifications based on the tag or index address corresponding to a virtual or physical address. They are PIPT, VIVT, PIVT, VIPT that is, physically indexed physically tagged, virtually indexed virtually tagged, physically indexed virtually tagged, virtually indexed physically tagged respectively.
13. What does DMA stand for?
A. direct memory access
B. direct main access
C. data main access
D. data memory address
Answer: A
The DMA is direct memory access that can modify the memory without the help of the processor. If any kind of memory access by DMA is to be done, it will pass a request to the processor bus and the processor provides an acknowledgment and gives them control of the bus to the DMA.
13. Which of the following cache has a separate comparator for each entry?
A. direct-mapped cache
B. fully associative cache
C. 2-way associative cache
D. 16-way associative cache
Answer: B
A fully associative cache has a comparator for each entry so that all the entries can be tested simultaneously.
14. What is the disadvantage of a fully associative cache?
A. hardware
B. software
C. memory
D. peripherals
Answer: A
The major disadvantage of the fully associative cache is the amount of hardware needed for the comparison increases in proportion to the cache size and hence, limits the fully associative cache.
15. How many comparators are present in the direct mapping cache?
A. 3
B. 2
C. 1
D. 4
Answer: C
The direct mapping cache has only one comparator so that only one location possibly has all the data irrespective of the cache size.
16. Which mapping of cache is inefficient from a software viewpoint?
A. fully associative
B. 2 way associative
C. 16 way associative
D. direct mapping
Answer: D
The direct mapping cache organization is simple from the hardware design aspect but it is inefficient from the software viewpoint.
17. Which mechanism splits the external memory storage into memory pages?
A. index mechanism
B. burst mode
C. distributive mode
D. a software mechanism
Answer: A
The indexing mechanism splits the external memory storage into a series of memory pages in which each page is the same size as the cache. Each page is mapped to the cache so that each page can have its own location in the cache.
18. Which of the following cache mapping can prevent bus thrashing?
A. fully associative
B. direct mapping
C. n way set associative
D. 2 way associative
Answer: C
Only one data can be accessed through indirect mapping that is, if one word is accessed at a time, all other words are discarded at the same time. This is known as bus thrashing which can be solved by splitting up the caches so there are 2,4,..n possible entries available. The major advantage of the set-associative cache is its capability to prevent the bus from thrashing at the expense of hardware.
19. Which cache mapping has a sequential execution?
A. direct mapping
B. fully associative
C. n way set associative
D. burst fill
Answer: D
The burst fill mode of cache mapping has a sequential nature of executing instructions and data access. The instruction fetches and execution accesses to sequential memory locations until it has a jump instruction or a branch instruction. This kind of cache mapping is seen in the MC68030 processor.
20. Which address is used for a tag?
A. memory address
B. logical address
C. cache address
D. location address
Answer: B
The cache memory uses either a physical address or a logical address for its tag data. For a logical cache, the tag refers to a logical address and for a physical cache, the tag refers to the physical address.