Electrical Properties of MOS and BiCMOS Circuits MCQ Quiz – Objective Question with Answer for Electrical Properties of MOS and BiCMOS Circuits MCQ MCQ
A. low input impedance
B. high input impedance
C. high output impedance
D. high input and output impedance
Answer: A
The inverter has low input impedance. The basic inverter circuit requires a transistor with the source connected to the ground and a load resistor connected from the drain to the positive supply Vdd.
62. The inverter has __________
A. low output impedance
B. low input impedance
C. low power dissipation
D. high input and output impedance
Answer: A
The inverter has low output impedance and low input impedance. These are some of the properties of a BiCMOS inverter.
63. The inverter has __________
A. high current driving capability
B. occupies a smaller area
C. high noise margin
D. all of the mentioned
Answer: D
The inverter has a high current driving capability, occupies a smaller area, and has high noise margins.
64. Output voltage swing should be reduced for a better performance of the BiCMOS circuit.
A. true
B. false
Answer: A
For a better performance BiCMOS circuit, the output voltage swing should be reduced. The possible maximum output peak-to-peak voltage obtained without clipping is called an output voltage swing.
65. BiCMOS inverter requires high load current sourcing.
A. true
B. false
Answer: A
BiCMOS inverter needs high load current sinking and sourcing. Sinking provides a grounded connection to the load, whereas sourcing provides a voltage source to the load.
66. BiCMOS has _______ standby leakage current.
A. higher
B. lower
C. very low
D. none of the mentioned
Answer: A
BiCMOS has a higher standby leakage current and thus has high power consumption.
67. For improved base current discharge ________ enhancement type nMOS devices have to be added.
A. two
B. three
C. one
D. four
Answer: A
For improved base current discharge, two enhancement type nMOS transistors have to be added.
68. The BJTs in the BICMOS circuit is in _____________ configuration.
A. Push-pull
B. Totem pole
C. Active high
D. Active low
Answer: B
In the BiCMOS circuit, the BJT transistors are in a Totem pole configuration.
69. The MOSFETS are arranged in this configuration to provide __________
A. Zero static power dissipation
B. High Input impedance
C. Both zero static power dissipation and high input impedance
D. None of the mentioned
Answer: C
MOSFETs provide zero static power dissipation and high input impedance.
70. In latch-up condition, parasitic component gives rise to __________ conducting path.
A. low resistance
B. high resistance
C. low capacitance
D. high capacitance
Answer: A
In latch-up conditions, the parasitic component gives rise to low resistance conducting path between Vdd and Vss with disastrous results. Careful control during fabrication is necessary to avoid this problem.
