1. The work function difference is negative for ____________
A. silicon substrate
B. polysilicon gate
C. silicon substrate & polysilicon gate
D. none of the mentioned
Answer: C
The work function difference between the gate and Si (Φms) is negative for silicon substrate and polysilicon gate.
2. Substrate bias voltage is positive for nMOS.
A. true
B. false
Answer: B
Substrate bias voltage Vsb is positive for pMOS and negative for nMOS.
3. According to body effect, substrate is biased with respect to ___________
A. source
B. drain
C. gate
D. Vss
Answer: A
According to the body effect, the substrate is biased with respect to the source. The body effect can be seen as a change in the threshold voltage
.
4. Increasing Vsb _______ the threshold voltage.
A. does not effect
B. decreases
C. increases
D. exponentially increases
Answer: C
Increasing the substrate bias voltage Vsb increases the threshold voltage because it depletes the channel of charge carriers.
5. Transconductance gives the relationship between ___________
A. input current and output voltage
B. output current and input voltage
C. input current and input voltage
D. output current and output voltage
Answer: B
Transconductance expresses the relationship between output current Ids and input voltage Vgs.
6. Transconductance can be increased by ___________
A. decreasing the width
B. increasing the width
C. increasing the length
D. decreasing the length
Answer: B
The transconductance gm of a MOS device can be increased by increasing its width and it does not depend on length.
7. Increasing the transconductance ___________
A. increases input capacitance
B. decreasing area occupied
C. decreasing input capacitance
D. a decrease in the output capacitance
Answer: A
Increasing the transconductance gm results in an increase in input capacitance and area occupied as it is directly proportional.
8. Ids is _______ to length L of the channel.
A. directly proportional
B. inversely proportional
C. not related
D. logarithmically related
Answer: B
Ids are inversely proportional to the length L of the channel and using this relationship strong dependence of output conductance on channel length can be demonstrated.
9. Switching speed of a MOS device depends on ___________
A. gate voltage above a threshold
B. carrier mobility
C. length channel
D. all of the mentioned
Answer: D
The switching speed of a MOS device depends on gate voltage above a threshold and on carrier mobility and inversely as the square of channel length.
10. A fast circuit requires ___________
A. high gm
B. low gm
C. does not depend on gm
D. low cost
Answer: A
A fast circuit requires gm as high as possible as the switching speed depends on gate voltage above the threshold and on carrier mobility and inversely to the square of channel length.
11. Surface mobility depends on ___________
A. effective drain voltage
B. effective gate voltage
C. channel length
D. effective source voltage
Answer: B
Surface mobility is dependent on the effective gate voltage (Vgs-Vt). Electron mobility on an oriented n-type inversion layer surface is larger than that on an oriented surface.
12. What is a MOS transistor?
A. minority carrier device
B. majority carrier device
C. majority & minority carrier device
D. none of the mentioned
Answer: B
MOS transistor is a majority carrier device, in which current in a conducting channel between the source and drain is modulated by a voltage.
13. The MOS transistor is non conducting when?
A. zero source bias
B. zero threshold voltage
C. zero gate bias
D. zero drain bias
Answer: C
The MOS transistor normally is at cut-off or becomes non-conducting with zero gate bias (gate voltage-source voltage).
14. Inverters are essential for ________
A. NAND gates
B. NOR gates
C. sequential circuits
D. all of the mentioned
Answer: D
Inverters are needed for restoring logic levels for NAND and NOR gates, and sequential and memory circuits.
15. In basic inverter circuit _____________ is connected to ground.
A. source
B. gates
C. drain
D. resistance
Answer: A
A basic inverter circuit consists of the transistor with a source connected to the ground and a load resistor connected from the drain to the positive supply rail Vdd.
16. In inverter circuit ________ transistors are used as the load.
A. enhancement mode
B. depletion-mode
C. all of the mentioned
D. none of the mentioned
Answer: B
Depletion mode transistors are preferred to be used as a load in inverter circuits as it occupies a lesser area and is produced on the silicon substrate, unlike resistors.
17. For the depletion-mode transistor, the gate should be connected to ________
A. source
B. drain
C. ground
D. positive voltage rail
Answer: A
For the depletion-mode transistor, the gate is connected to the source so it is always on and only the characteristic curve Vgs=0 is relevant.
18. In nMOS inverter configuration depletion mode device is called as ________
A. pull up
B. pull down
C. all of the mentioned
D. none of the mentioned
Answer: A
In nMOS inverter configuration, depletion mode devices are called pull up and enhancement mode devices are called pull-down transistors.
19. What is the ratio of Zp.u/Zp.d?
A. 1/4
B. 4/1
C. 1/2
D. 2/1
Answer: B
The ratio of Zp.u/Zp.d, where Z is determined by the length to width ratio of the transistor, is given by 4/1.
20. Pass transistors are transistors used as ________
A. switches connected in series
B. switches connected in parallel
C. inverters used in series
D. inverter used in parallel
Answer: A
Pass transistors are transistors used as switches in series with lines carrying logic levels due to the isolated nature of the gate.
21. An inverter driven through one or more pass transistors has a Zp.u/Zp.d ratio of ________
A. 1/4
B. 4/1
C. 1/8
D. 8/1
Answer: D
An inverter driven directly from the output of another has the ratio of 4/1 and if driven through one or more pass transistors has the ratio of 8/1.
22. In depletion mode pull-up, dissipation is high since current flows when?
A. Vin = 1
B. Vin = 0
C. Vout = 1
D. Vout = 0
Answer: A
In nMOS depletion-mode pull-up, dissipation is high since current flows Vin = logical 1.
23. In complementary transistor pull-up, current flows when?
A. Vin = 1
B. Vin = 0
C. current doesn’t flow
D. Vout = Vin
Answer: C
In complementary transistor pull-up no current flows either for logical 1 or 0, full logical 1 and 0 levels are presented at the output.
24. CMOS inverter has ______ regions of operation.
A. three
B. four
C. two
D. five
Answer: D
CMOS inverter has five distinct regions of operation which can be determined by plotting CMOS inverter current versus Vin.
25. If the n-transistor conducts and has a large voltage between source and drain, then it is said to be in _____ region.
A. linear
B. saturation
C. non-saturation
D. cut-off
Answer: B
If the n-transistor conducts and has a large voltage between source and drain, then it is in saturation.
26. If the p-transistor is conducting and has a small voltage between source and drain, then it is said to work in ________
A. linear region
B. saturation region
C. non-saturation resistive region
D. cut-off region
Answer: C
If the p-transistor is conducting and has a small voltage between source and drain, then it is said to be in the unsaturated resistive region.
27. In the region where inverter exhibits gain, the two transistors are in the _______ region.
A. linear
B. cut-off
C. non-saturation
D. saturation
Answer: D
In the region where the inverter exhibits gain, the two transistors n and p operate in the saturation region.
28. If both the transistors are in saturation, then they act as ________
A. current source
B. voltage source
C. divider
D. buffer
Answer: A
When both the transistors are in saturation, they act as current sources so that the equivalent circuit is two current sources between Vdd and Vss.
29. If βn = βp, then Vin is equal to ________
A. Vdd
B. Vss
C. 2Vdd
D. 0.5Vdd
Answer: D
If βn = βp, then Vin = 0.5Vdd which implies that the changeover between logic levels is symmetrically disposed about the point.
