# Pseudo-Random Test Pattern MCQ Quiz – Objective Question with Answer for Pseudo-Random Test Pattern Generation in VLSI

1. Which exhibits low fault coverage?

A. random test pattern
B. pseudo-random test pattern
C. deterministic test pattern
D. algorithmic test pattern

The circuit under test exhibits low fault coverage when tested with the pseudo-random test generation method.

2. Large AND function will produce _______ infrequently.

A. logic 0
B. logic 0 and logic 1
C. logic 1
D. neither logic 0 or 1

The large AND function produces logic 1 infrequently due to its equally likelihood of more 0’s whereas the large OR function produces logic 0 infrequently.

3. The circuit which incorporates _______ can be tested with a weighted pseudo-random test pattern.

A. preset
B. reset
C. clear
D. break

The circuit under test which incorporates global reset or preset can be tested with a pseudo-random test pattern method.

4. Circuits with global reset have fault coverage in the range of

A. 5% to 10%
B. 11% to 15%
C. 15% to 20%
D. 6% to 8%

The circuit under test with global reset has fault coverage as low as 11% to 15% due to its fault detection blocking effect.

5. The probability of a given bit in LFSR being logic 0 is

A. 0
B. 1
C. 0.25
D. 0.5

The probability of a given bit in LFSR being logic 0 is approximately 0.5 and NANDing two bits of LFSR gives the probability as 0.25.

6. Initialization of the test pattern generator to all 1’s generate

A. global reset
B. clear
C. toggle
D. buffer

The initialization of the test pattern generator to all 1’s generates a global reset or preset during the first test vector for the initialization of the circuit under test.

7. Reset signal weight is given as

A. 2m
B. 2(-m)
C. 2m
D. 2(-m)

The rule of thumb is to make the reset signal weight as 2(-m) where m is chosen to be greater than the sequential depth of the circuit under test.

8. The sequential depth is the number of

A. OR gates
B. AND gates
C. flip flops
D. EX-OR gates

The sequential depth of the circuit under test is the number of flip flops in the longest path between primary input and output.

9. AND gate is used to ensure whether the test patterns have sufficient clock cycles.

A. true
B. false

NAND gate or NOR gate helps to ensure whether the test patterns have sufficient clock cycles to propagate through the circuit under test before the reset occurs.

10. Which method has more area overhead?

A. random test pattern
B. pseudo-random test pattern
C. algorithmic test pattern
D. deterministic test pattern