VLSI Fault Model MCQ Quiz – Objective Question with Answer for Fault Model in VLSI

21. The defect present in the following MOSFET is:

A. Logical stuck at 1
B. Logical stuck at 0
C. Physical defect
D. Electrical Transistor stuck open

Answer: D

The dimensions of the gate are less than the distance between source and drain.

22. The fault simulation detects faults by:

A. Test generation
B. Construction of fault Dictionaries
C. Design analysis under faults
D. All of the mentioned

Answer: D

The fault simulation detects faults by

Test generation
Construction of fault Dictionaries
Design analysis under faults

23. The ease with which the controller establishes specific signal values at each node by setting input values is known as:

A. Testability
B. Observability
C. Controllability
D. Manufacturability

Answer: C

Controllability is defined as the ease with which the controller establishes a specific signal values at each node by setting input values.

24. The ease with which the controller determines signal value at any node by setting input values is known as:

A. Testability
B. Observability
C. Controllability
D. Manufacturability

Answer: B

Observability is defined as the ease with which the controller determines signal value at any node by setting input values.

25. The poor controllability circuits are:

A. Decoders
B. Clock generators
C. Circuits with feedback
D. All of the mentioned

Answer: D

The poor controllability circuits are due to

Decoders
Clock generators
Circuits with feedback

26. The circuits with poor observability are:

A. ROM
B. PLA
C. Sequential circuits with long feedback loops
D. All of the mentioned

Answer: C

The circuits with poor observability are sequential circuits with long feedback loops.

27. A Large number of input vectors are used to set a particular node (1) or (0), to propagate an error at the node to output making the circuit low on:

A. Testability
B. Observability
C. Controllability
D. All of the mentioned

Answer: A

The circuit is said to be low on Testability if the large number of input vectors are used to set a particular node (1) or (0), to propagate an error at the node to output.

28. Divide and Conquer approach to large and complex circuits for testing is found in:

A. Partition and Mux Technique
B. Simplified automatic test pattern generation technique
C. Scan based technique
D. All of the mentioned

Answer: A

The divide and Conquer approach to large and complex circuits for testing is found in the partition and Mux technique.

29. LSSD stands for:
A. Linear system synchronous detection
B. Level sensitive system detection
C. Level sensitive scan design
D. Level sensitive scan detection

Answer: C

LSSD stands for Level sensitive scan design. The level-sensitive scan design technique was developed and pioneered by IBM and forms the basis for a structured approach to the design of testable circuits.

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