11. In BiCMOS, the analysis of the operation of BJT is well explained by ___________
A. RC Model
B. Emitter resister model
C. Ebers Moll Model
D. Hybrid model
Answer: C
In BiCMOS, the analysis of the operation of BJT is well explained by Ebers Moll Model.
12. In latch-up condition, parasitic component gives rise to __________ conducting path.
A. low resistance
B. high resistance
C. low capacitance
D. high capacitance
Answer: A
In latch-up conditions, the parasitic component gives rise to low resistance conducting path between Vdd and Vss with disastrous results. Careful control during fabrication is necessary to avoid this problem.
13. Latch-up can be induced by __________
A. incident radiation
B. reflected radiation
C. etching
D. diffracted radiation
Answer: A
Latch-up can be induced by glitches on the supply rail or by incident radiation.
14. How many transistors might bring up a latch-up effect in the p-well structure?
A. two
B. three
C. one
D. four
Answer: A
Two transistors and two resistances might bring up the latch-up effect in the p-well structure. These are associated with p-well and with regions of the substrate.
15. Substrate doping level should be decreased to avoid the latch-up effect.
A. true
B. false
Answer: B
An increase in substrate doping level with a consequent drop in the value of Rs can be used as a remedy for the latch-up problem.
16. What can be introduced to reduce the latch-up effect?
A. latch-up rings
B. guard rings
C. latch guard rings
D. substrate rings
Answer: B
The introduction of guard rings can reduce the effect of the latch-up problem. Guard rings are diffusions that decouple the parasitic bipolar transistors.
17. Which process produces a circuit that is less prone to the latch-up effect?
A. CMOS
B. nMOS
C. pMOS
D. BiCMOS
Answer: D
BiCMOS process produces circuits that are less likely to suffer from latch-up problems whereas CMOS circuits are very highly prone to latch-up problems.
18. Which one of the following is the main factor for reducing the latch-up effect?
A. reduced p-well resistance
B. reduced n-well resistance
C. increased n-well resistance
D. increased p-well resistance
Answer: B
One of the main factors in reducing the latch-up effect is reduced n-well resistance Rw. Reduction in Rw means that a larger lateral current is necessary to invite latch-up and a higher value of holding current is also required.
19. The parasitic PNP transistor has the effect of _______ carrier lifetime.
A. increasing
B. decreasing
C. exponentially decreasing
D. exponentially increasing
Answer: B
The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region.
20. The reduction in carrier lifetime brings about __________
A. reduction in alpha
B. reduction in beta
C. reduction in current
D. reduction in voltage
Answer: B
The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region which results in radiation in beta.
21. To reduce the latch-up effect substrate resistance should be high.
A. true
B. false
Answer: B
To reduce the latch-up effect, substrate resistance Rs should be low. Reduction of Rs and Rw means that a larger lateral current is necessary to invite a latch-up.
22. Latch-up is the generation of __________
A. low impedance path
B. high impedance path
C. low resistance path
D. high resistance path
Answer: A
Latch-up is the generation of the low-impedance path in CMOS chips between the power supply and ground rails.
23. Latch-up is brought about by BJTs __________
A. with positive feedback
B. with negative feedback
C. with no feedback
D. without BJT
Answer: A
Latch-up occurs due to BJTs for silicon-controlled rectifiers with positive feedback and virtually short-circuit the power and ground rail.
24. Sudden transient in power can cause latch-up.
A. true
B. false
Answer: A
Sudden transient in power and ground buses are also among the reason which causes the latch-up effect.
25. BJT gain should be ______ to avoid the latch-up effect.
A. increased
B. decreased
C. should be maintained constant
D. changed randomly
Answer: B
BJT gain should be reduced by lowering the minority carrier lifetime through doping of the substrate to lower the latch-up effect.