# Noise Margin in VLSI MCQ Quiz – Objective Question with Answer for Noise Margin in VLSI

1. Noise Margin is:

A. Amount of noise the logic circuit can withstand
B. Difference between VOH and VIH
C. Difference between VIL and VOL
D. All of the Mentioned

Noise Margin is defined as the amount of noise the logic circuit can withstand, it is given by the difference between VOH and VIH or VIL and VOL.

2. The VIL is found from the transfer characteristics of the inverter by:

A. The point where the straight line at VOH ends
B. The slope of the transition at a point at which the slope is equal to -1
C. The midpoint of the transition line
D. All of the mentioned

The VIL is the input voltage at which the slope of the transition will be equal to -1.

3. The VIH is found from the transfer characteristic of the inverter by:

A. The point where a straight line at VOH ends
B. The slope of the transition at a point at which the slope is equal to -1
C. The midpoint of the transition line
D. All of the mentioned

The VIH is the input voltage at which the slope of the transition will be equal to -1. In Transfer characteristics at 2 points, we will find the slope to be -1.

4. The relation between threshold voltage and Noise Margin is:

A. Vth = sqrt(Noise Margin)
B. Vth = NMH – NML
C. Vth = (NMH+NML)/2
D. None of the mentioned

The relation between threshold voltage and Noise Margin is VOH – VIH

5. The Lower Noise Margin is given by:

A. VOL – VIL
B. VIL – VOL
C. VIL ~ VOL(Difference between VIL and VOL, depends on which one is greater)
D. All of the Mentioned

The Lower Noise Margin is given by

Noise margin = VIL-VOL.

6. The Higher Noise Margin is given by:

A. VOH – VIH
B. VIH – VOH
C. VIH ~ VOH(Difference between VIH and VOH, depends on which one is greater)
D. All of the mentioned

The Higher Noise Margin is given by

Noise margin = VOH – VIH.

7. The Uncertain or transition region is between:

A. VIH and VOH
B. VIL and VOL
C. VIH and VIL
D. VOH and VOL

In Input, the uncertain region is VIH and VIL.

8. The noise immunity ____________ with noise margin.

A. Decreases
B. Increases
C. Constant
D. None of the Mentioned

The noise immunity is directly proportional to the noise margin.

9. If VIL of the 2nd gate is higher than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as:

A. Logic input 1
B. Uncertain
C. Logic input 0
D. None of the mentioned

Logic output 0 from the first gate is considered as logic input 0 at the second gate as it lies within the range.

10. If VIL of the 2nd gate is lower than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as:

A. Logic input 1
B. Uncertain
C. Logic input 0
D. None of the mentioned

The level of the output signal from 1st gate is higher than the range for low input at 2nd gate. So it is uncertain.

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