21. Using _____ long wires is possible.
A. silicide
B. metal
C. polysilicon
D. diffusion
Answer: A
Using silicide, reasonable long wires are possible. It is a modest RC product. Silicides are used in place of polysilicon in some nMOS processes.
22. One pass transistor can be driven through the output of another.
A. true
B. false
Answer: B
No pass transistor gate must be driven through the output of one or more pass transistors since logic 1 levels are degraded by the threshold voltage.
23. Pass transistors are allowed to be constructed under
A. diffusion layer
B. polysilicon layer
C. metal layer
D. silicon layer
Answer: C
Pass transistors are allowed to be constructed under metal layers to save space and be more convenient.
24. Maximum allowable current density in aluminum is
A. 0.1 mA/µm2
B. 0.5 mA/µm2
C. 2 mA/µm2
D. 1 mA/µm2
Answer: D
The maximum allowable current density in the aluminum wire is 1 mA/µm2. Otherwise, metal migration may occur.
25. In which design all circuitry and all interconnections are designed?
A. full custom design
B. semi-custom design
C. gate array design
D. transistor design
Answer: A
Full custom design is the complete design for the implementation. It contains all circuitry and all interconnections/communication paths.
26. Which design contains only the interconnections designed?
A. full custom design
B. semi-custom design
C. gate array design
D. transistor design
Answer: C
Gate array design which is also known as uncommitted logic array design has the design of only the interconnections/communication paths.
27. In which method regularity is used to reduce complexity?
A. random approach
B. hierarchical approach
C. algorithmic approach
D. semi-design approach
Answer: B
The hierarchical approach is the one in which principles of iteration or regularity can be used to reduce the complexity of the design task.
28. Size of the die is determined using
A. transistor size
B. inverter size
C. area of the circuitry
D. length of the circuitry
Answer: C
The size of the die is determined by the area occupied by the circuitry. Large die sizes are associated with poor yields and high costs.
29. Which design is faster?
A. full custom design
B. semi-custom design
C. gate array design
D. transistor design
Answer: C
Gate array design is faster than a prototype full-custom design and the final custom designs must be carefully optimized.
30. Which has relatively low-level capabilities?
A. hand-crafted designs
B. computer-assisted textual entry
C. computer-assisted graphical entry
D. silicon compiler-based design
Answer: B
Computer-assisted textual entry has programs that may be relatively low-level capabilities and it allows the entry of rectangular boxes, wires, etc.
