# VLSI Storage Element MCQ Quiz – Objective Question with Answer for VLSI Storage Element

1. Which clock is preferred in storage devices?

A. single-phase overlapping clock signal
B. single-phase non-overlapping clock signal
C. two-phase overlapping clock signal
D. two-phase non-overlapping clock signal

The two-phase non-overlapping clock signal is easily available and works better and more effectively and this clock will be used throughout the storage system.

2. Clock signal Φ2 is to

A. write data
C. refresh data
D. store data

Bits or data written into storage elements may be assumed to be settled before the immediately following signal Φ2 refreshes stored data where appropriate.

A. before Φ1
B. after Φ1
C. before Φ2
D. after Φ2

Bits of data may be read from storage elements on the next of Φ1 clock signal that is read signals RD are Anded with Φ1.

4. Factors for assessment of storage elements are

A. volatility
B. non-volatility
C. number of bits
D. data repeatability

Some of the comparative assessment factors for storage elements are area requirement, estimated dissipation per bit stored, and volatility.

5. Which occupies a lesser area?

A. nMOS
B. pMOS
C. CMOS
D. BiCMOS

nMOS design with buried contacts needs a lesser area than CMOS design and this can be estimated by calculating the space stored by each bit in the register cell.

6. In which design, dissipation is less?

A. nMOS
B. pMOS
C. CMOS
D. BiCMOS

In CMOS design, static dissipation is very small since only the switching dissipation will be significant, particularly at high speeds.

7. The impedance of the pull-down transistor in nMOS can be given as

A. 2Rs
B. 4Rs
C. 1/2 Rs
D. 1/4 Rs

Each inverter stage has an 8:1 ratio and in the nMOS register cell, at least one inverter should always be on and Zp.u. is given as 4Rs, and Zp.d. is given as 1/2Rs.

8. Data storage time is

A. 1 millisecond
B. 1 second
C. 1 minute
D. 10 seconds

Data is stored by the charge on the gate capacitance of each inverter stage, so that data storage time is limited to 1 msec or less.

9. A bit is read at T1 when

A. RD is low, WR is low
B. RD is high, WR is low
C. RD is low, WR is high
D. RD is high, WR is high

With RD control line low, a bit can be read through clock period T1 when WR is made high. After reading the bit WR is made low.

10. A bit can be stored when

A. RD is low, WR is low
B. RD is high, WR is low
C. RD is low, WR is high
D. RD is high, WR is high