11. Current flows only when
A. RD is low
B. RD is high
C. RD raises exponentially high
D. RD comes exponentially down
Answer: B
Current flows only when RD is high and 1 is stored. Thus static dissipating is nil.
12. Overhead bits are used for sensing.
A. true
B. false
Answer: A
Overhead bits are used for sensing. Some amount of overhead bits is used in the one-transistor dynamic memory cell.
13. Reading a cell is a _______ operation.
A. constructive
B. destructive
C. semi constructive
D. semi destructive
Answer: B
Reading a cell is a destructive operation and the stored bit must be rewritten every time it is read.
14. RAM is a _____ cell.
A. dynamic
B. partially dynamic
C. static
D. pseudo-static
Answer: D
RAM is a pseudo-static cell. It stores data indefinitely and refreshing is not necessary.
15. Pseudo static RAM cell is built using
A. one inverter
B. two inverters
C. three inverters
D. four inverters
Answer: B
Pseudo static RAM cell is built using two inverters and data can be stored in these two inverters by connecting it in parallel and using feedback.
16. Cells must be non-stackable in RAM storage cell.
A. true
B. false
Answer: B
Cells must be stackable, both side by side and from top to bottom. This must be carefully considered when the layout is made.
17. Which cell is non-volatile?
A. one-transistor dynamic cell
B. two-transistor dynamic cell
C. four transistor dynamic cell
D. pseudo static RAM cell
Answer: D
Pseudo-static RAM cell is a non-volatile cell. It is used for long time storage. Non-volatile memory is also called long-term memory.
18. In RAM arrays, the transistor is of
A. minimum size
B. maximum size
C. of any size
D. size doesn’t play a role
Answer: A
In RAM arrays, the transistor is of minimum size and thus it is incapable of sinking large charges quickly.
19. Which implementation is slower?
A. NAND gate
B. NOR gate
C. AND gate
D. OR gate
Answer: B
NOR gate implementation is slower even though both NAND and NOR gate implementation are suitable for CMOS.
20. FOR nMOS which implementation is not suitable?
A. NAND gate
B. NOR gate
C. AND gate
D. OR gate
Answer: A
In nMOS, NAND gate implementation is impractical because of the large number of gates requiring three or more inputs.
