VLSI Wiring Capacitance MCQ Quiz – Objective Question with Answer for VLSI Wiring Capacitance

21. Sheet resistance of semiconductor is directly measured using ___________

A. Ohmmeter
B. Four-point probe measurement
C. Non-contact eddy current based testing device
D. Any of the mentioned

Answer: B

The sheet resistance of semiconductors is directly measured using a Four-point probe measurement.

 

22. The resistance of the semiconductor material is 800Ω. The sheet resistance if the dimensions of the material is 0.125µm wide and 1 mm long is?

A. 10 Ω/square
B. 0.01 Ω/square
C. 0.10 Ω/square
D. 1 Ω/square

Answer: C

We know that R=Rs(L/W).
Therefore Rs=R × W/L
Substituting the values of R, W and L, Rs is found to be 0.10 Ω/square.

 

23. The typical values of sheet resistance for the n-well semiconductor is ________

A. 1-5 KΩ/square
B. 10-50 KΩ/square
C. 1-5 Ω/square
D. 100-500 Ω/square

Answer: A

The n-well semiconductors have high sheet resistance in the range of 1-5 KΩ/square.

 

24. The typical values of sheet resistance for polysilicon semiconductors is?

A. 15-30 Ω/square
B. 150-300 Ω/square
C. 1.5-3 KΩ/square
D. 0.15-0.3 Ω/square

Answer: A

The typical value of polysilicon semiconductors is 15-30 Ω/square.

 

25. For λ based design, what is the standard unit of capacitance, (λ=5µm)?

A. 0.01pF
B. 0.0032pF
C. 0.0023pF
D. All of the mentioned

Answer: A

5 µm × 5 µm × 4 pF × 10-4/µm2 = 0.01pF.

 

26. If the standard area is 2λ × 2λ, then the standard capacitance of a gate of length 30λ and width 6λ is?

A. 180oCg
B. 45oCg
C. 90oCg
D. 4oCg

Answer: B

30λ × 6λ/2λ × 2λ = 45°Cg.

 

27. Which of the following mainly constitutes the output node capacitance?

A. Inter electrode capacitance
B. Stray capacitance
C. Junction Parasitic capacitance
D. All of the mentioned

Answer: C

Output node capacitance mainly consists of junction parasitic capacitance.

 

28. The junction parasitic capacitance are produced due to ____________

A. Source diffusion regions
B. Gate diffusion regions
C. Drain diffusion region
D. All of the mentioned

Answer: C

The junction parasitic capacitance is produced due to drain diffusion capacitance.

 

29. The amount of parasitic capacitance at the output node is determined by __________

A. Concentration of the impurity-doped
B. Size of the total drain diffusion area
C. Charges stored in the capacitor
D. None of the mentioned

Answer: B

The amount of parasitic capacitance is a linear function of the drain diffusion area.

 

30. The dominant component of the total output capacitance in submicron technology is?

A. Drain diffusion capacitance
B. Gate oxide capacitance
C. Interconnect capacitance
D. Junction parasitic capacitance

Answer: C

Interconnect capacitance becomes a dominant component in submicron technology.

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