A. boron oxide
B. silicon oxide
C. silicon nitride
D. boron nitride
Answer: D
The growth of gallium arsenide crystals from high purity boron nitride cubicles is becoming the primary growth technique.
2. Wafers in GaAs fabrication are thermally unstable.
A. true
B. false
Answer: B
The fabrication of GaAs includes the production of round wafers and they are thermally stable and have superior semi-insulating properties.
3. The sequence of the steps followed in the fabrication of GaAs is
A. lapping
B. polishing
C. grinding
D.All of the above
Answer: D
The steps followed in the fabrication of GaAs are grinding the As-grown boules, wafering, edge rounding, lapping, polishing, and then wafer scrubbing.
4. Which devices are fabricated using a planar process?
A. enhancement mode MESFET
B. depletion mode MESFET
C. enhancement mode MOSFET
D. depletion-mode MOSFET
Answer: B
The depletion-mode devices are fabricated using a planar process where n-type dopants are directly implanted into semi-insulating GaAs.
5. Threshold voltage can be varied by
A. varying impurity concentration
B. varying doping level
C. varying channel length
D. varying source voltage
Answer: B
Threshold voltage in GaAs can be varied by varying the channel thickness and the doping level of the active region.
6. Stable native oxide was produced by
A. oxidation of silicon
B. oxidation of gallium
C. oxidation of boron
D. oxidation of aluminum
Answer: A
The driving force of silicon technology was brought about as the result of the presence of stable native oxide which was readily produced through the oxidation of silicon.
7. In GaAs technology, deposited dielectric films bring about
A. passivation
B. combination
C. decomposition
D. diffusion
Answer: A
In GaAs technology, due to the absence of a stable native oxide deposited dielectric films bring about passivation or encapsulation.
8. Formation of the n-active layer is achieved by
A. indirect ion implantation
B. direct ion implantation
C. liquifying
D. wafering
Answer: B
The formation of the n-active layer is achieved by direct ion implantation into the GaAs semi-insulating substrate through the insulating layer.
9. Implantation of ________ is done for the formation of source and drain.
A. n- layer
B. n+ layer
C. p- layer
D. p+ layer
Answer: B
Implantation of a deep low resistivity n+ layer is done for the formation of source and drain and n-layer for the formation of the channel layer.
10. The channel resistance is high for
A. source contact
B. drain contact
C. gate contact
D. source and drain contacts
Answer: D
The channel resistance is in the order of 1000 to 2500 ohm/square which is too high for source and drains contacts.
