1. Reduction in power dissipation can be brought by

A. increasing transistor area

B. decreasing transistor area

C. increasing transistor feature size

D. decreasing transistor feature size

2. When does the longest delay occur in 8:1 inverters?

A. during 1 to 0 transition

B. during 0 to 1 transition

C. during faster speed

D. delays are always short

3. In inverter during logic 1 to 0 transition, capacitance discharges at

A. pull-up resistance

B. pull-down resistance

C. both pull-up and pull-down

D. at gate

4. In minimum size nMOS 8:1 inverter, the logic 0 to 1 transition delay is given as

A. 5Ʈ

B. 20Ʈ

C. 40Ʈ

D. 50Ʈ

5. In minimum size nMOS 8:1 inverter, the logic 1 to 0 transition delay is given as

A. 5Ʈ

B. 20Ʈ

C. 40Ʈ

D. 50Ʈ

6. For a regular 8:1 inverter, the transition delay is given as

A. 10Ʈ

B. 20Ʈ

C. 21Ʈ

D. 25Ʈ

7. The area of the CMOS inverter is proportional to

A. area of n device

B. area of p device

C. total area of n and p device

D. square of minimum feature size

8. The ratio of Wp/Wn can be given as

A. 1:2

B. 2:1

C. 1:1

D. 2:2

9. Switching power dissipation can be given as

A. Cl × Vdd × f

B. Vdd2 × f

C. Cl × Vdd2

D. Cl × Vdd2 × f

10. Load capacitance can be minimized by

A. increasing A

B. decreasing A

C. increasing Psd

D. does not depend on A

11. Rise time and fall time can be equalized by

A. βn = βp

B. βn = 2βp

C. βp = 2βn

D. βn = 1/2βp

12. Rise time and fall time can be also equalized by

A. Lp = Ln = λ

B. Lp = Ln = λ/2

C. Lp = Ln = 2λ

D. 2Lp = Ln = λ

13. Equalizing of rise time and the fall time is possible in

A. nMOS

B. pseudo nMOS

C. CMOS

D. pMOS

14. High and low noise margins can be equalized by

A. βn = βp

B. βn greater than βp

C. βn lesser than βp

D. Lp = 2Ln

15. Inverter pair delay D is given as equal to

A. tr

B. tf

C. tr-tf

D. tr+tf

16. For minimum D consider

A. Ln = Lp = 2λ

B. Ln greater than Lp = 2λ

C. Lp greater than Ln

D. Lp = 2Ln

17. Different parameter optimization is easily achievable in

A. nMOS

B. pMOS

C. pseudo nMOS

D. CMOS

18. Minimizing A with respect to Wp.d. gives

A. Wp.d. = 2λ

B. Wp.d. = λ/2

C. Wp.d. = (k)1/2 × 2λ

D. Wp.d. = k × (λ)^{1/2} × 2

19. Using Zp.u./Zp.d = k, Lp.u. can be obtained as

A. k × 2λ

B. k × λ

C. (k)1/2 × 2λ

D. k × 2 × (λ)^{1/2}

20. Minimum area can be given as

A. 4 × Ao × λ × (k)^{1/2}

B. 4 × Ao × λ × k

C. 8 × Ao × λ2 × (k)^{1/2}

D. 8 × Ao × λ × (k)^{1/2}

21. When Zp.d. or Zp.u. increases, delay

A. increases

B. decreases

C. remains the same

D. delay becomes zero

22. For minimum D which relation is chosen?

A. Zp.u. = 1/2k

B. Zp.u. = k

C. Zp.d. = 1/k

D. Zp.d. = 1

23. Noise margin measures the changing strength of

A. input voltage

B. output voltage

C. threshold voltage

D. supply voltage

24. Which has better noise margins?

A. nMOS

B. pMOS

C. CMOS

D. BiCMOS

25. A 4-bit processor has two buses which are

A. unidirectional

B. bidirectional

C. one unidirectional and one bidirectional

D. more than two buses

26. The IN and OUT bus lines relative positions are interchanged to

A. match height

B. match length

C. match width

D. match thickness

27. The IN and OUT bus lines should be in

A. metal

B. polysilicon

C. diffusion

D. silicon

28. Extensions are

A. vertical

B. horizontal

C. diagonal

D. haphazard

29. Rifts and extensions should be placed in

A. The minimum amount of geometry

B. The maximum amount of geometry

C. in slopes

D. anywhere in the layout

30. Rifts are used for smooth flow through buses.

A. true

B. false

31. Input and output pads are made up of

A. polysilicon

B. metal

C. silicon

D. carbon

32. Bonding pads are placed

A. in the chip

B. exactly at the center of the chip

C. edge of the chip

D. above the chip

33. Which pad contains Schmitt trigger circuitry?

A. Vdd pads

B. Vss pads

C. input pads

D. output pads

34. Which occupies a lesser area?

A. Vdd pads

B. Vss pads

C. input pads

D. output pads

35. Buffers are needed to drive

A. small capacitance

B. large capacitance

C. small resistance

D. large resistance

36. Pads must be placed generally in the periphery of the chip area.

A. true

B. false

37. How much area should be allocated for pads?

A. one third

B. two-third

C. half

D. three fourth

38. Which provides large capacitance?

A. load capacitance

B. bus wiring capacitance

C. sheet capacitance

D. area capacitance

39. Bus wiring capacitance is driven through

A. one transistor

B. two transistors

C. three transistors

D. no transistors

40. What is the delay of input pads?

A. 5Ʈ

B. 10Ʈ

C. 40Ʈ

D. 30Ʈ

41. The total delay for the select register circuit is

A. 33Ʈ

B. 60Ʈ

C. 55Ʈ

D. 73Ʈ

42. Delay for data propagation is

A. 10 nsec

B. 50 nsec

C. 100 nsec

D. 150 nsec

43. Which is the longest delay in the adder process?

A. sum delay

B. carry delay

C. propagation delay

D. inverter delay

44. The total delay for the adder process is

A. 100 nsec

B. 200 nsec

C. 220 nsec

D. 250 nsec

45. The refreshing clock period should propagate through

A. memory cell

B. wiring

C. carry chain

D. any subunit

46. The value of Ʈ for 5-micron technology is always constant.

A. true

B. false

47. The total clock period for the adder process is

A. 100 nsec

B. 150 nsec

C. 200 nsec

D. 250 nsec

48. The Zp.u./Zp.d. ratio for the nMOS inverter is

A. 4:1

B. 3:1

C. 1:4

D. 1:3

49. The impedance ratio for pseudo-nMOS is

A. 4:1

B. 3:1

C. 1:4

D. 1:3

50. What is the value of peripheral capacitance for 5-micron technology?

A. 4 × 10^{(-4)} pf/µm^{2}

B. 5 × 10^{(-4)} pf/µm^{2}

C. 8 × 10^{(-4)} pf/µm^{2}

D. 12 × 10^{(-4)} pf/µm^{2}