Built-in self-test aims to A. reduce test pattern generation cost B. reduce the volume of test data C. reduce test time D. all of the mentioned 2. In the data compression technique, the comparison is done on A. test response B. entire test data C. data inputs D. output sequences Answer: A In the …
1. The major difficulty in sequential circuit testing is in A. determining output B. determining an internal state C. determining the external state D. determining input combinations 2. The design technique helps in improving A. controllability B. observability C. controllability and observability D. overall performance 3. A sequential circuit contains combinational logic and …
VLSI Scan Design Technique MCQ – Objective Question with Answer for Biotechnology Read More »
1. Practical guidelines for testability aim at A. facilitating test generation B. facilitating test application C. avoiding timing problems D. all of the mentioned 2. When a node is difficult to access A. sub-nodes are formed B. internal pads are added C. external pads are added D. circuit is subdivided 3. The additional …
1. Sequential circuits are represented as A. finite state machine B. infinite state machine C. finite synchronous circuit D. infinite asynchronous circuit 2. Sequential circuit includes A. delays B. feedback C. delays and feedback from the input to output D. delays and feedback from output to input 3. Which constitutes the test vectors …
1. The input signal combination in exhaustive testing is given as A. 2N B. 21/N C. 2(M+N) D. 1/2N 2. Observability is the process of A. checking all inputs B. checking all outputs C. checking all possible inputs D. checking errors and performance 3. Exhaustive testing is suitable when N is A. small …
1. Circuit nodes cannot be probed for monitoring or excitation. A. true B. false 2. The circuit should be tested at A. design level B. chip level C. transistor level D. switch level 3. ______ of the area is dedicated for testability. A. 20% B. 10% C. 30% D. 25% 4. Partitioning …
1. Simulator converts circuit information to A. design plan B. does verification C. set of equations D. floor plan 2. The electrical behaviour of a circuit is given using A. design rules B. floor plan C. structures and layouts D. mathematical modelling 3. Which gives the main electrical behaviour of various parts of …
VLSI Simulator MCQ Quiz – Objective Question with Answer for VLSI Simulator Read More »
1. Physical verification tools in the design process include A. circuit extractors B. textual entry C. graphical entry D. simulation 2. Behavioral tools contain A. graphical entry B. design check C. performance check D. simulation 3. Simulators are available for A. transistor-level logic B. switch level logic C. gate-level logic D. design level …
1. Physical verification tools in the design process include A. circuit extractors B. textual entry C. graphical entry D. simulation 2. Behavioral tools contain A. graphical entry B. design check C. performance check D. simulation 3. Simulators are available for A. transistor-level logic B. switch level logic C. gate-level logic D. design level …
VLSI CAD Tools MCQ Quiz – Objective Question with Answer for VLSI CAD Tools Read More »
1. Caltech intermediate form code is a A. low-level graphic language B. low-level textual language C. high-level graphic language D. high-level textual language 2. CIF generates code that is A. high-level language B. assembly level language C. machine-readable language D. very high-level language 3. CIF code is compatible with A. low system geometry B. …
VLSI CIF Layout Design MCQ Quiz – Objective Question with Answer for VLSI CIF Layout Read More »
